Abstract: A multiple-stage splitter/combiner circuit includes first and second splitter/combiner circuits coupled together. The first splitter/combiner circuit has first, second, and third input/output (I/O) ports, a first quarter wave line with a first end coupled to the first I/O port and a second end coupled to the second I/O port, a second quarter wave line with a first end coupled to the first I/O port and a second end coupled to the third I/O port, and a first resistor with first and second terminals coupled to the second and third I/O ports, respectively. The second splitter/combiner circuit has fourth, fifth, and sixth I/O ports, and a ring of multiple quarter wave lines, which includes third and fourth quarter wave lines. The third and fourth quarter wave lines each extend from the fourth I/O port in different directions from each other to the fifth and sixth I/O ports, respectively.
Type:
Grant
Filed:
December 15, 2021
Date of Patent:
October 15, 2024
Assignee:
NPX B.V.
Inventors:
Jasper Pijl, Mark Pieter van der Heijden
Abstract: A chip card (1) comprises a chip card controller (3), a display (6), a display driver (5) operatively coupled to the chip card controller (3) and to the display (6), a user input device (12), and a user input interface (13) operatively coupled to the user input device (12). The user input device (12) is configured to turn on and/or turn off at least parts of the chip card (1) and is an integral part of the display driver (5).
Abstract: A method of manufacturing an inductor embedded into a semiconductor chip package (100) is described, which method comprises providing a carrier (102; 202; 302) having, between a first side and an opposite second side, a first conductive layer (104; 503), an intermediate layer (205; 505), a second conductive layer (106; 504), forming an inductor and contact pads for the chip by patterning the first conductive layer (104; 503) from the first side of the carrier (102; 202; 302), assembling the chip and providing an encapsulation (514) and forming terminals of the package, by patterning the second conductive layer (106; 504) from the second side of the carrier.