Abstract: It is provided a circuit for generating finger print code data comprising: plural pairs of first transistors, each of the first transistors having a source formed in the substrate, a drain formed in the substrate, a channel formed in the substrate between the source and the drain, a gate insulating layer formed on the channel, a gate electrode formed over the gate insulating layer, and an insulating sidewall formed at a side surface of the gate electrode; plural pairs of cross coupled second transistors, each of the plural pairs of cross coupled second transistors having drains and commonly connected sources, corresponding to each of the plural pairs of first transistors; and plural pairs of third transistors, each of the plural pairs of third transistors corresponding to each of the plural pairs of cross coupled second transistors.

Abstract: A nonvolatile memory cell includes a first-conductivity-type silicon substrate, a metal layer formed in a surface of the first-conductivity-type silicon substrate, a second-conductivity-type diffusion layer formed in the surface of the first-conductivity-type silicon substrate and spaced apart from the metal layer, an insulating film disposed on the surface of the first-conductivity-type silicon substrate between the metal layer and the second-conductivity-type diffusion layer, a gate electrode disposed on the insulating film between the metal layer and the second-conductivity-type diffusion layer, and a sidewall disposed at a same side of the gate electrode as the metal layer and situated between the gate electrode and the metal layer, the sidewall being made of insulating material.

Abstract: A nonvolatile memory cell includes a first-conductivity-type silicon substrate, a metal layer formed in a surface of the first-conductivity-type silicon substrate, a second-conductivity-type diffusion layer formed in the surface of the first-conductivity-type silicon substrate and spaced apart from the metal layer, an insulating film disposed on the surface of the first-conductivity-type silicon substrate between the metal layer and the second-conductivity-type diffusion layer, a gate electrode disposed on the insulating film between the metal layer and the second-conductivity-type diffusion layer, and a sidewall disposed at a same side of the gate electrode as the metal layer and situated between the gate electrode and the metal layer, the sidewall being made of insulating material.

Abstract: A nonvolatile memory device includes a pair of MIS transistors one of which is placed in a programmed state by a first program operation utilizing a hot carrier effect to store one-bit data in the pair of MIS transistors, and a control unit configured to recall the one-bit data from the pair of MIS transistors in a recall operation, to cause an unprogrammed one of the MIS transistors to be placed in a programmed state by a second program operation utilizing a hot carrier effect in response to the one-bit data recalled from the pair of MIS transistors, and to erase the programmed states of both of the MIS transistors in an erase operation.

Abstract: A nonvolatile memory device includes a word line, four or more bit lines, three or more MIS transistors having gate nodes thereof connected to the word line, the N-th (N: positive integer) one of the MIS transistors having two source/drain nodes thereof connected to the N-th and N+1-th ones of the bit lines, respectively, a sense circuit having two nodes and configured to amplify a difference between potentials of the two nodes, and a switch circuit configured to electrically couple the N-th and N+2-th ones of the bit lines to the two nodes of the sense circuit, respectively, and to electrically couple the N+1-th one of the bit lines to a fixed potential, for any numerical number N selected to detect single-bit data stored in the N-th and N+1-th ones of the MIS transistors.

Abstract: A nonvolatile memory device includes a word line, four or more bit lines, three or more MIS transistors having gate nodes thereof connected to the word line, the N-th (N: positive integer) one of the MIS transistors having two source/drain nodes thereof connected to the N-th and N+1-th ones of the bit lines, respectively, a sense circuit having two nodes and configured to amplify a difference between potentials of the two nodes, and a switch circuit configured to electrically couple the N-th and N+2-th ones of the bit lines to the two nodes of the sense circuit, respectively, and to electrically couple the N+1-th one of the bit lines to a fixed potential, for any numerical number N selected to detect single-bit data stored in the N-th and N+1-th ones of the MIS transistors.

Abstract: A nonvolatile semiconductor memory device includes an MIS transistor having nodes, a control circuit configured to apply a first set of potentials to the nodes to cause an irreversible change in transistor characteristics, to apply a second set of potentials to the nodes to cause a first current to flow through the MIS transistor in a first direction, and to apply the second set of potentials to the nodes to cause a second current to flow through the MIS transistor in a second direction opposite the first direction, and a sense circuit configured to produce a signal responsive to a difference between the first current and the second current.

Abstract: A nonvolatile memory device includes one or more reference cell transistors, one or more memory cell transistors, and a current source circuit including three or more field effect transistors that have gates thereof connected together, the three or more field effect transistors including two or more field effect transistors and another field effect transistor, currents flowing through the two or more field effect transistors being combined to flow through the one or more reference cell transistors, and another field effect transistor having a drain thereof connected to one of the one or more memory cell transistors.

Abstract: A nonvolatile semiconductor memory device includes an MIS transistor having nodes, a control circuit configured to apply a first set of potentials to the nodes to cause an irreversible change in transistor characteristics, to apply a second set of potentials to the nodes to cause a first current to flow through the MIS transistor in a first direction, and to apply the second set of potentials to the nodes to cause a second current to flow through the MIS transistor in a second direction opposite the first direction, and a sense circuit configured to produce a signal responsive to a difference between the first current and the second current.

Abstract: A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix and each configured to store data, and a test circuit configured to output to outside the semiconductor memory device an output signal indicative of an amount of test current flowing through a selected one of the plurality of memory cell transistors, wherein the test circuit includes a plurality of reference cell transistors employed to successively produce varying amounts of currents, a comparison circuit configured to successively compare the amount of test current with each of the varying amounts of currents, and a code generating circuit configured to generate a code indicative of a result of the successive comparisons performed by the comparison circuit, wherein the code is output as the output signal.

Abstract: A nonvolatile memory device includes a pair of PMOS transistors, and a control circuit configured to operate in a store mode to apply to a first one of the PMOS transistors potentials that cause an NBTI degradation purposefully and to apply to a second one of the PMOS transistors potentials that cause no NBTI degradation while causing no current to flow between a source node and a drain node of the first one of the PMOS transistors, and to operate in a recall mode to set gate nodes of the PMOS transistors to a common potential to detect a difference in the NBTI degradation between said PMOS transistors.

Abstract: A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor in a first operation such that a lingering change is created in transistor characteristics of the MIS transistor in response to the data stored in the latch, wherein the MIS transistor includes a highly-doped substrate layer, a lightly-doped substrate layer disposed on the highly-doped substrate layer, diffusion regions formed in the lightly-doped substrate layer, a gate electrode, sidewalls, and an insulating film.

Abstract: A memory circuit includes a latch having a first node and a second node, a MIS transistor having a gate node, a first source/drain node coupled to the first node of the latch, and a second source/drain node, and a control circuit configured to control the gate node and second source/drain node to make a lingering change in a threshold voltage of the MIS transistor in a first operation and to cause the latch in a second operation to store data responsive to whether a lingering change in the threshold voltage is present, wherein the MIS transistor includes diffusion regions, a gate electrode, and sidewalls, wherein a metallurgical junction of each of the diffusion regions is positioned under the gate electrode, and a lateral boundary of a depletion layer in the diffusion region serving as a drain is positioned under a corresponding one of the sidewalls in the first operation.

Abstract: A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch.

Abstract: A nonvolatile semiconductor memory device includes a latch circuit having two nodes, a nonvolatile memory cell including two MIS transistors, a bit swapping unit configured to provide straight connections between the two nodes and the two MIS transistors during a first operation mode and to provide cross connections between the two nodes and the two MIS transistors during a second operation mode, and a control circuit configured to cause, in one of the first and second operation modes, the nonvolatile memory cell to store the data latched in the latch circuit as an irreversible change of transistor characteristics occurring in a selected one of the two MIS transistors, and further configured to cause, in another one of the first and second operation modes, the latch circuit to detect the data stored in the nonvolatile memory cell.

Abstract: A nonvolatile semiconductor memory device includes a latch circuit including a first inverter and a second inverter cross-coupled to each other, a source node of a MIS transistor of the first inverter and a source node of a MIS transistor of the second inverter being both coupled to a plate line, and a control circuit configured to apply a first potential to the plate line in a store mode to cause a change in threshold voltage to one of the MIS transistors, and configured to apply a second potential to the plate line in a power-on mode to cause the latch circuit to latch data responsive to the change in threshold voltage generated in the store mode, such that the data latched by the latch circuit in the power-on mode is automatically output to outside the nonvolatile semiconductor memory device upon power-on thereof.

Abstract: A nonvolatile semiconductor memory device includes a latch circuit including a first inverter and a second inverter cross-coupled to each other, a source node of a MIS transistor of the first inverter and a source node of a MIS transistor of the second inverter being both coupled to a plate line, and a control circuit configured to apply a first potential to the plate line in a store mode to cause a change in threshold voltage to one of the MIS transistors, and configured to apply a second potential to the plate line in a power-on mode to cause the latch circuit to latch data responsive to the change in threshold voltage generated in the store mode, such that the data latched by the latch circuit in the power-on mode is automatically output to outside the nonvolatile semiconductor memory device upon power-on thereof.

Abstract: A nonvolatile semiconductor memory device includes a first latch to store data, a nonvolatile memory cell including two MIS transistors to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors selected in response to the data stored in the first latch, a second latch to store data obtained by sensing a difference in the transistor characteristics between the two MIS transistors, a logic circuit to produce a signal indicative of comparison between the data of the first latch and the data of the second latch, and a control circuit configured to repeat a store operation storing data in the nonvolatile memory cell, a recall operation storing data in the second latch, and a verify operation producing the signal indicative of comparison until the signal indicates that the data of the first latch and the data of the second latch are the same.

Abstract: A nonvolatile semiconductor memory device includes a latch configured to store data, a plurality of word lines, a driver configured to activate one of the plurality of word lines, and a plurality of nonvolatile memory cells coupled to the respective word lines, each of the nonvolatile memory cells coupled to the latch so as to exchange stored data with the latch upon activation of a corresponding one of the word lines, each of the nonvolatile memory cells including two MIS transistors and configured to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors, wherein the driver includes at least one nonvolatile memory cell storing count data responsive to a number of times storing of data has been performed with respect to the plurality of nonvolatile memory cells, and is configured to activate one of the word lines indicated by the count data.

Abstract: A nonvolatile semiconductor memory device includes a nonvolatile memory cell including an odd number of MIS transistor pairs, each of which stores one-bit data by creating an irreversible change of transistor characteristics in one of the two paired MIS transistors, latches equal in number to the odd number of MIS transistor pairs to store the odd number of one-bit data recalled from the MIS transistor pairs, the recalling of the one-bit data of a given MIS transistor pair being performed by sensing a difference in the transistor characteristics between the two paired MIS transistors of the given MIS transistor pair, and a majority decision circuit configured to make a majority decision based on the odd number of one-bit data to determine a bit value of the nonvolatile memory cell.