Abstract: In a phase sync circuit (40) which extracts a clock signal CK from a data signal D in a random NRZ format, particularly in a phase sync circuit (40) of a dual loop configuration including both a phase comparison circuit (81) and a frequency comparison circuit (10), a phase sync circuit (40) capable of achieving both broadening of the capture range and extraction of a high-quality clock signal without requiring any reference clock signal is provided. A clock signal Ca, another clock signal Cb having a phase delayed by an approximately ¼ period from the clock signal Ca and the data signal D are input to the frequency comparison circuit (10) to output a logical value according to the high-low relationship between the frequency of the clock signal and the bit rate of the data signal D.

Abstract: A silicon substrate is prepared by furnishing a silicon substrate (10) having a step (11) of at least 5 &mgr;m high on one surface, forming by high pressure heat oxidation an oxide film (12) which is thinner than the step, and removing the oxide film on the higher surface region until the silicon surface is exposed in the higher surface region while leaving the oxide film on the lower surface region. Because of excellent electrical properties, minimized warpage, a substantially constant oxygen concentration, and a definitely ascertainable oxide-silicon boundary, the silicon substrate is suitable for use in optical waveguide devices.

Abstract: An automatic dynamic range control circuit is provided with a fixed-gain first circuit means and a variable-gain second circuit means having substantially the same propagation delay as the first circuit means. The automatic dynamic range control circuit holds the peak value of an input signal, selects the first circuit means when this peak value is smaller than a reference signal level, and selects the second circuit means when the peak value exceeds this reference signal level. When the held peak value is smaller than the reference signal level, the second circuit means is operated at the same gain relative to an input signal as the first circuit means by having its gain set by the reference signal. When the held peak value exceeds the reference signal, the gain of the second circuit means is limited by this held peak value and its output level is kept at or below a prescribed level.