Abstract: An error correction circuit (20) according to this invention includes a first error correction processing circuit (21) configured to perform error correction processing in a row direction on array data having undergone first coding in the row direction, an error detection processing circuit (26) configured to perform error detection processing in a column direction on the array data having undergone second coding in the column direction, a corrected-bit likelihood calculation circuit (24) configured to calculate for each row the sum of likelihoods of corrected bits each of which is a bit corrected by the first error correction processing circuit (21), a high-likelihood row detection circuit (25) configured to detect rows of the array data in the descending order of the sums of likelihoods of corrected bits of respective rows output from the corrected-bit likelihood calculation circuit (24), and a second error correction processing circuit (27) configured to correct a bit at which a column error-detected by th

Abstract: A data transfer circuit according to the invention includes a memory configured to write data in accordance with a write pointer in synchronization with a first clock, and read out the data in accordance with a readout pointer in synchronization with a second clock, a clock generation circuit configured to generate the second clock by multiplying a reference clock by a rational number N, a frequency error estimation circuit configured to estimate a frequency error between the first clock and the second clock based on a change amount of a pointer difference between the write pointer and the readout pointer, and an adjustment circuit configured to output, as an adjustment multiple ?N, a value obtained by dividing the estimated frequency error by a frequency of the reference clock. The clock generation circuit generates the second clock by multiplying the reference clock by a rational number (N+?N).

Abstract: A frame synchronization system (1) according to this invention includes a frame signal generation circuit (20) configured to generate a frame signal including a plurality of first frame signals each including a first frame synchronization signal and a first payload signal, wherein the first frame synchronization signal is formed from at least one symbol and is set with an average amplitude lower than an average amplitude of the first payload signal, and a frame synchronization circuit (60) configured to receive the frame signal via an optical transmission path (70), and detect the first frame synchronization signal from a received signal, wherein the received signal is divided into frames having a symbol length of the first frame signal, coordinate values, on an IQ plane, of the signals at identical symbol positions of the plurality of divided frames are added over the plurality of frames, and a symbol specified by magnitude comparison in the frame based on an addition result is determined as the first frame

Abstract: A light shielding structure of an optical circuit of the present invention uses a part of the structure of the light reception element itself to suppress stray light. A stepped electrode that covers an upper surface and side surface of a first semiconductor layer constituting a light absorption portion of the light reception element is formed at a height substantially equal to that of an optical waveguide in the optical circuit, and the light absorption portion of the light reception element is shielded from stray light by a wall-shaped or column-shaped wiring electrode extending substantially perpendicularly to a surface layer of the optical circuit. The light shielding structure of the present invention uses a part of the configuration of the light reception element, is formed integrally with the light reception element, and also has an aspect of the invention of the light reception element.

Abstract: Ensuring that a control program of a programmable electronic component included in an optical module updatable as well while a control program of a microprocessor included in the optical module is in operation. A module that functions by causing an electronic component to operate, a microprocessor located in the module and coupled to a host device via communicating device uses data in the S-record format downloaded from the host device using the communicating device to update a control program of the electronic component.

Abstract: A tap-coefficient control circuit sets the tap coefficient converged by the second tap coefficient updater as an initial value of the tap coefficient in the first digital filter which is to be updated by the first tap coefficient updater, arranges the tap coefficients converged by the second tap coefficient updater in descending order of contribution degree to the convergence operation of tap coefficient update in the first tap coefficient updater, judges the tap coefficient not less than upper specified number to be valid and the tap coefficient less than the specified number to be invalid, and sets the tap coefficient of the first digital filter corresponding to the tap coefficient judged to be invalid to zero not to be used in a calculation of the first tap coefficient updater until a next judgment result is made.

Abstract: First compensation circuitry includes a first digital filter compensating a phase difference between a phase of a symbol of a received signal and a sampling timing, and first filter coefficient calculation circuitry calculating a filter coefficient of the first digital filter as a first filter coefficient. Second filter coefficient calculation circuitry calculates, as a second filter coefficient, a filter coefficient for adaptive equalization that compensates distortion due to temporally changing polarization dispersion, based on an output of the first digital filter. Coefficient combination circuitry combines the first filter coefficient and the second filter coefficient. Second compensation circuitry includes a second digital filter which uses a filter coefficient combined by the coefficient combination circuitry and performs a compensation of the phase difference between the phase of the symbol of the received signal and the sampling timing, and a process of the adaptive equalization at the same time.

Abstract: Part of compensation of the transmission characteristics of the optical transmitter is performed by transmitter compensation circuitry disposed at a stage prior to the optical transmitter. Remaining part of compensation of the transmission characteristics of the optical transmitter and compensation of the transmission characteristics of the optical receiver is performed by a receiver compensation circuitry disposed at a stage subsequent to the optical receiver. Transmitter compensation characteristics of the transmitter compensation circuitry is set so that a peak-to-average-power ratio of an output signal from the transmitter compensation circuitry becomes equal to or smaller than a predetermined value.

Abstract: An arithmetic circuit includes a LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and distributed arithmetic circuits (2-m) that calculate values z[m] that are sums of products of data x[m, n] of a data set X[m] containing M pairs of data x[m, n] and the coefficients c[n], in parallel for each of the M pairs. The distributed arithmetic circuit (2-m) includes binomial distributed arithmetic circuits that, for each of the pairs, calculate sums of products of a value obtained by pairing N data x[m, n] corresponding to the circuit two by two and a value obtained by pairing the coefficients c[n] two by two, and a figure matching circuit that matches a number of decimal figures of the sums with a predetermined number of decimal figures.

Abstract: A computation unit subtracts a prediction image from an input image. An orthogonal transformation unit applies orthogonal transformation to an output of the computation unit. A quantization unit quantizes an output of the orthogonal transformation unit. An encoding unit encodes an output of the quantization unit. A prediction mode determination unit determines a prediction mode from the input image. The prediction mode is different according to types of an I-picture, a P-picture and a B-picture.

Abstract: An arithmetic circuit includes an LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and a distributed arithmetic circuit (2-m) that calculates values y[m] of product-sum arithmetic, by which data x[m, n] of a data set X[m] containing M pairs of data x[m, n] is multiplied by the coefficients c[n] and the products are summed up, in parallel for each of the M pairs.

Abstract: Part of compensation of the transmission characteristics of the optical transmitter is performed by transmitter compensation circuitry disposed at a stage prior to the optical transmitter. Remaining part of compensation of the transmission characteristics of the optical transmitter and compensation of the transmission characteristics of the optical receiver is performed by a receiver compensation circuitry disposed at a stage subsequent to the optical receiver. Transmitter compensation characteristics of the transmitter compensation circuitry is set so that a peak-to-average-power ratio of an output signal from the transmitter compensation circuitry becomes equal to or smaller than a predetermined value.

Abstract: An optical module of a configuration that ensures use of commercially available electronic components and reduction of the number of current generation circuits and electric wirings. The optical module includes an electronic component mounted on a separate board from a light wave circuit board provided with an optical component such as an optical switch, and they are each electrically connected by wire bonding. For this reason, the optical module can use a commercially available electronic component. In addition, the module has a configuration in which heaters of optical switches, which do not simultaneously flow currents, are grouped and a current from one current generation circuit is supplied to any one of the heaters in the group by means of one electrical switch. For this reason, the optical module does not have to be prepared with the same number of electrical switches and current generation circuits as the number of heaters.

Abstract: An error correction device includes a first correction unit which performs error correction decoding of data by a repetitive operation, having a full operation state in which the error correction decoding is repeated until convergence is obtained and a save operation state in which the number of times of the repetitive operation is restricted to a predetermined number. An error information estimation unit estimates an input error rate or an output error rate of the first correction unit using a decoding result of the first correction unit, and a control unit which controls transition between the full operation state and the save operation state based on at least one piece of information of the input error rate, the output error rate, and an operation time of the first correction unit. It is thus possible to provide an error correction device that can improve a transmission characteristic while suppressing power consumption.

Abstract: A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination.

Abstract: An optical module that has a structure ensuring reduction in size. The optical module has a structure where a part of a fiber block is protruded from a housing. By including a thin plate, this optical module can avoid entering of dust in the housing, allows a position shift of the fiber block due to a mounting position error of an optical component in the housing, a position shift of an opening portion due to a dimensional error of the housing, or a displacement due to a temperature change, and can reduce the coupling loss due to the optical axis misalignment.

Abstract: There is provided a small MCS with the number of leads reduced by half as compared with the conventional configuration. A multicast switch according to the present invention is formed on a substrate, comprising: M input ports, N output ports; M×N optical switch units (optical SU); optical waveguides optically connecting the M input ports, M×N optical SU, and N output ports; and leads connected to the respective M×N optical SU. A multicast switch is configured such that by activating one optical SU, an optical signal input to an input port associated with the activated optical SU is output from an output port associated with the activated optical SU. The M×N optical SU include at least a gate switch and a main switch. In each optical SU, the gate switch and the main switch are connected to the common lead.

Abstract: A process of estimating a transfer function or an inverse transfer function of the optical transmitter from first data obtained by the optical receiver when a first known signal is transmitted from the transmitter to the receiver, and a temporary transfer function or a temporary inverse transfer function of the optical receiver, is performed for multiple frequency offsets between the optical transmitter and the optical receiver. At this time, the transfer function or the inverse transfer function of the optical transmitter is estimated by comparing the first data obtained by compensating at least one or none of a temporary transfer function of the optical receiver and transmission path characteristics detected in the receiver, with a first known signal before transmission to which what is not compensated for the first data between the temporary transfer function of the optical receiver and the transmission path characteristic is added.

Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).

Abstract: A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination.