Abstract: The invention relates to a snoop filter device, a node controller, a multicomponent computer system, a computer-implemented method, a data processing system and a computer-readable storage medium aiming at enabling improved tracking of a scalable number of cache elements in multiprocessor systems. The invention involves scaling of a snoop filter device according to the number of cache elements that it is desireable to track.
Type:
Application
Filed:
February 9, 2023
Publication date:
April 3, 2025
Applicant:
Numascale AS
Inventors:
Thibaut Palfer-Sollier, Steffen Persvold, Helge Simonsen, Mario Lodde, Thomas Moen, Einar Rustad, Goutam Debnath, Kai Arne Midjas
Abstract: A cache coherent node controller at least includes one or more network interface controllers, each network interface controller includes at least one network interface, and at least two coherent interfaces each configured for communication with a microprocessor. A computer system includes one or more of nodes wherein each node is connected to at least one network switch, each node at least includes a cache coherent node controller.
Type:
Grant
Filed:
June 4, 2018
Date of Patent:
October 4, 2022
Assignee:
Numascale AS
Inventors:
Thibaut Palfer-Sollier, Einar Rustad, Steffen Persvold
Abstract: The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.
Type:
Grant
Filed:
April 30, 2018
Date of Patent:
March 23, 2021
Assignee:
Numascale AS
Inventors:
Einar Rustad, Helge Simonsen, Steffen Persvold, Goutam Debnath, Thomas Moen
Abstract: The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.
Type:
Application
Filed:
April 30, 2018
Publication date:
March 19, 2020
Applicant:
Numascale AS
Inventors:
Einar Rustad, Helge Simonsen, Steffen Persvold, Goutam Debnath, Thomas Moen
© 2025 Justia
