Patents Assigned to Numascale AS
  • Snoop filter device
    Patent number: 11755485
    Abstract: The invention relates to a device for use in maintaining cache coherence in a multiprocessor computing system. The snoop filter device is connectable with a plurality of cache elements, where each cache element comprises a number of cache agents. The snoop filter device comprises a plurality of snoop filter storage locations, where each snoop filter storage location is mapped to one cache element.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: September 12, 2023
    Assignee: NUMASCALE AS
    Inventors: Thibaut Palfer-Sollier, Steffen Persvold, Helge Simonsen, Mario Lodde, Thomas Moen, Kai Arne Midjås, Einar Rustad, Goutam Debnath
  • Digital circuit testing and analysis module, system and method thereof
    Patent number: 11688482
    Abstract: The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 27, 2023
    Assignee: NUMASCALE AS
    Inventors: Thibaut Palfer-Sollier, Einar Rustad, Steffen Persvold
  • Coherent node controller
    Patent number: 11461234
    Abstract: A cache coherent node controller at least includes one or more network interface controllers, each network interface controller includes at least one network interface, and at least two coherent interfaces each configured for communication with a microprocessor. A computer system includes one or more of nodes wherein each node is connected to at least one network switch, each node at least includes a cache coherent node controller.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 4, 2022
    Assignee: Numascale AS
    Inventors: Thibaut Palfer-Sollier, Einar Rustad, Steffen Persvold
  • Programmable cache coherent node controller
    Patent number: 11157405
    Abstract: A computer system includes a first group of CPU modules operatively coupled to at least one first Programmable ASIC Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second Programmable ASIC Node Controller connected to a second group of CPU modules running a single instance of an operating system.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: October 26, 2021
    Assignee: NUMASCALE AS
    Inventors: Einar Rustad, Helge Simonsen, Steffen Persvold, Goutam Debnath, Thomas Moen
  • Cache coherent node controller for scale-up shared memory systems having interconnect switch between a group of CPUS and FPGA node controller
    Patent number: 10956329
    Abstract: The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 23, 2021
    Assignee: Numascale AS
    Inventors: Einar Rustad, Helge Simonsen, Steffen Persvold, Goutam Debnath, Thomas Moen
  • CACHE COHERENT NODE CONTROLLER FOR SCALE-UP SHARED MEMORY SYSTEMS
    Publication number: 20200089612
    Abstract: The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.
    Type: Application
    Filed: April 30, 2018
    Publication date: March 19, 2020
    Applicant: Numascale AS
    Inventors: Einar Rustad, Helge Simonsen, Steffen Persvold, Goutam Debnath, Thomas Moen