Patents Assigned to NUMEM INC.
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Patent number: 11967366Abstract: A memory includes an array with rows and columns of memory cells. The rows include a first row and a second row. The memory also includes a plurality of logic gates in the array. Each logic gate of the plurality of logic gates includes a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output. The memory further includes a plurality of sense lines in the array. The output of each logic gate of the plurality of logic gates is coupled to a sense line of the plurality of sense lines.Type: GrantFiled: July 21, 2022Date of Patent: April 23, 2024Assignee: NUMEM INC.Inventor: Bindiganavale S. Nataraj
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Patent number: 11901000Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.Type: GrantFiled: August 4, 2022Date of Patent: February 13, 2024Assignee: NUMEM INC.Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Patent number: 11829775Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.Type: GrantFiled: July 28, 2022Date of Patent: November 28, 2023Assignee: NUMEM Inc.Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Patent number: 11443802Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.Type: GrantFiled: July 9, 2020Date of Patent: September 13, 2022Assignee: NUMEM INC.Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Patent number: 11436025Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.Type: GrantFiled: July 9, 2020Date of Patent: September 6, 2022Assignee: NUMEM INC.Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Publication number: 20220013169Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Applicant: NUMEM Inc.Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Publication number: 20220012063Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Applicant: NUMEM Inc.Inventors: Eric Hall, Doug Smith, Nicholas T. Hendrickson, Jack Guedj
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Patent number: 10726880Abstract: An apparatus for storing data in a magnetic random access memory (MRAM) is provided. The MRAM may store data in one or more resistance-based memory cells and may include a plurality of comparators to compare a voltage generated based on the resistance-based memory cells to a reference voltage to determine a stored logic state. In some implementations, the reference voltage may be generated by a plurality resistance-based memory cells. The reference voltage may be adjusted higher or lower by storing different logic states within the resistance-based memory cells.Type: GrantFiled: November 2, 2018Date of Patent: July 28, 2020Assignee: Numem Inc.Inventor: Nicholas T. Hendrickson
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Patent number: 10460056Abstract: Systems, methods and devices are disclosed that may a user to specify various layout and operational parameters of a resistive-based memory array in a manner that accommodates the unique characteristics of resistance-based memory cells and magnetic-based memory cells.Type: GrantFiled: May 28, 2019Date of Patent: October 29, 2019Assignee: NUMEM INC.Inventor: Nilesh A. Gharia
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Patent number: 10430534Abstract: Systems, methods and devices are disclosed that may a user to specify various layout and operational parameters of a resistive-based memory array in a manner that accommodates the unique characteristics of resistance-based memory cells and magnetic-based memory cells.Type: GrantFiled: November 29, 2017Date of Patent: October 1, 2019Assignee: NUMEM INC.Inventor: Nilesh A. Gharia