Patents Assigned to Numerical Technologies
  • Patent number: 6887630
    Abstract: A system for fracturing polygons on masks used in lithography processes for manufacturing an integrated circuit is described. The system fractures polygons that include cavities in either the horizontal edges or the vertical edges by examining the aspect ratio (length/width) of prospective slices made at each vertex of the polygon. After determining the aspect ratio of each prospective slice, the system selects the slice with the lowest aspect ratio and slices the polygon into two sub-polygons. Slicing the polygon in this manner effectively eliminates “slivers” or slices with extreme aspect ratios. This process is continued until each sub-polygon is either a rectangle or a trapezoid that can be printed by electron beam photolithography.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: May 3, 2005
    Assignee: Numerical Technologies
    Inventor: Bruce Luttrell
  • Patent number: 6859918
    Abstract: One embodiment of the invention provides a system and a method for reducing line end shortening during an optical lithography process for manufacturing an integrated circuit. The system operates by receiving a specification of the integrated circuit, wherein the specification defines transistors that include gates. Next, the system identifies a gate within the specification, wherein the gate includes an endcap that is susceptible to line end shortening during the optical lithography process. The system then extends a phase shifter used to form the gate, so that the phase shifter defines at least a portion of the endcap and thereby reduces line end shortening of the endcap due to optical effects.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: February 22, 2005
    Assignee: Numerical Technologies
    Inventors: Melody W. Ma, Hua-Yu Liu
  • Patent number: 6846617
    Abstract: One embodiment of the invention provides a system that uses pupil filtering to mitigate optical proximity effects that arise during an optical lithography process for manufacturing an integrated circuit. During operation, the system applies a photoresist layer to a wafer and then exposes the photoresist layer through a mask. During this exposure process, the system performs pupil filtering, wherein the pupil filtering corrects for optical proximity effects caused by an optical system used to expose the photoresist layer.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: January 25, 2005
    Assignee: Numerical Technologies
    Inventor: Christophe Pierrat
  • Patent number: 6821689
    Abstract: One embodiment of the present invention provides a system that uses an exposure through a second mask to assist an exposure through a phase shifting mask in printing a tight space adjacent to a large feature. During operation, the system exposes a photoresist layer on the surface of a semiconductor wafer through the phase-shifting mask. This phase-shifting mask includes phase shifters that define a space between a first feature and a second feature, wherein the first feature is so large that the effectiveness of phase shifting is degraded in defining the space. Moreover, the degradation in phase shifting and the tightness of the space cause the space not to print reliably when exposed through the phase shifting mask alone. To alleviate this problem the system exposes the photoresist layer through the second mask, wherein the exposure through the second mask assists in exposing the space between the first feature and the second feature so that the space prints reliably.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: November 23, 2004
    Assignee: Numerical Technologies
    Inventor: Christophe Pierrat
  • Publication number: 20040191650
    Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of assist features and proximity correction features. The method includes applying an adjustment to a phase shift mask pattern including a first and a second phase shift window, and a control chrome with a control width, and/or to a trim mask pattern having a trim shape with a trim width based upon one or both of a rule based correction and a model based correction to improve a match between a resulting exposure pattern and a target feature.
    Type: Application
    Filed: April 6, 2004
    Publication date: September 30, 2004
    Applicant: Numerical Technologies
    Inventor: Christophe Pierrat
  • Patent number: 6795955
    Abstract: One embodiment of the invention provides a system for speeding up processing of a layout of an integrated circuit that has been divided into cells. The system operates by determining if a target cell in the layout is identical to a preceding cell for which there exists a previously calculated solution by comparing an identifier created from the target cell with an identifier created from the preceding cell. If the target cell is identical to a preceding cell, the system uses the previously calculated solution as a solution for the target cell. Otherwise, if the target cell is not identical to the preceding cell, the system processes the target cell to produce the solution for the target cell. Note that this approach can also be used for a number of different processes, such as distributed fracturing or optical proximity correction.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: September 21, 2004
    Assignee: Numerical Technologies
    Inventors: Kevin D. MacLean, Roger W. Sturgeon
  • Publication number: 20030068564
    Abstract: An accurate, cost-effective system and method for correcting 3D effects on an alternating phase-shifting mask (PSM) is provided. To facilitate this correction, a library can be built to include a first group of 180 degree phase-shifting regions, wherein these regions have a common first size. Based on this first size, 3D simulation is performed. A transmission and a phase are altered in a 2D simulation based on this first size until a shape dependent transmission and a shape dependent phase allow the 2D simulation to substantially match the 3D simulation. Finally, a modified first size is chosen using the shape dependent transmission and the shape dependent phase such that a 2D simulation based on the modified first size substantially matches the 3D simulation based on the first size. The library associates the first size with the modified first size, the shape dependent transmission, and the shape dependent phase.
    Type: Application
    Filed: October 9, 2001
    Publication date: April 10, 2003
    Applicant: Numerical Technologies
    Inventors: Yong Liu, Hua-Yu Liu
  • Publication number: 20030023939
    Abstract: One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
    Type: Application
    Filed: July 26, 2001
    Publication date: January 30, 2003
    Applicant: Numerical Technologies
    Inventors: Christophe Pierrat, Chin-Hsen Lin, Yao-Ting Wang, Fang-Cheng Chang
  • Publication number: 20020164065
    Abstract: A simulated wafer image of a physical mask and a defect-free reference image are used to generate a severity score for each defect, thereby giving a customer meaningful information to accurately assess the consequences of using a mask or repairing that mask. The defect severity score is calculated based on a number of factors relating to the changes in critical dimensions of the neighbor features to the defect. A common process window can also be used to provide objective information regarding defect printability. Certain other aspects of the mask relating to mask quality, such as line edge roughness and contact corner rounding, can also be quantified by using the simulated wafer image of the physical mask.
    Type: Application
    Filed: March 20, 2001
    Publication date: November 7, 2002
    Applicant: Numerical Technologies
    Inventors: Lynn Cai, Linard Karklin, Linyong Pang
  • Publication number: 20020136964
    Abstract: A conductive blank enables election beam (e-beam) patterning rather than optical patterning for the phase level etch of a phase-shifting mask (PSM) photomask. The conductive blank includes a conductive layer between a chrome (pattern) layer and a quartz substrate. The chrome layer is patterned with in-phase and phased features, and then is recoated with a resist layer. An e-beam exposure tool exposes the resist layer over the phased features. The still intact conductive layer under the chrome layer dissipates any charge buildup in the resist layer during this process. A phase level etch then etches through the conductive layer and creates a pocket in the quartz. A subsequent isotropic etch through both the in-phase and phased features removes the conductive layer at the in-phase features and improves exposure radiation transmission intensity. Alternatively, a visually transparent conductive layer can be used, eliminating the need to etch through the in-phase features.
    Type: Application
    Filed: March 23, 2001
    Publication date: September 26, 2002
    Applicant: Numerical Technologies
    Inventor: Christophe Pierrat