Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to programming a non-volatile memory device.

Abstract: Subject matter disclosed herein relates to storing information via a NAND flash translation layer.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.

Abstract: Subject matter disclosed herein relates to validating memory content in persistent main memory of a processor.

Abstract: Subject matter disclosed herein relates to memory devices and security of same.

Abstract: Subject matter disclosed herein relates to techniques to read a memory cell that involve a threshold edge phenomenon of a reset state of phase change memory.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.

Abstract: Subject matter disclosed herein relates to a read operation process for a nonvolatile memory.

Abstract: According to a method for multilevel reading of a phase change memory cell a bit line (9) and a PCM cell (2) are first selected and a first bias voltage (VBL, V00) is applied to the selected bit line (9). A first read current (IRD00), that flows through the selected bit line (9) in response to the first bias voltage (VBL, V00), is compared with a first reference current (I00). The first reference current (I00) is such that the first read current (IRD00) is lower than the first reference current (I00), when the selected PCM cell (2) is in a reset state, and is otherwise greater. It is then determined whether the selected PCM cell (2) is in the reset state, based on comparing the first read current (IRD00) with the first reference current (I00). A second bias voltage (VBL, V01), greater than the first bias voltage (VBL, V00), is applied to the selected bit line (9) if the selected PCM cell (2) is not in the reset state.

Abstract: A method for accessing a phase change memory device, wherein a first sub-plurality of bitlines is grouped in a first group and a second sub-plurality of bitlines is grouped in a second group. At least a bitline in the first and second groups are selected; currents are supplied to the selected bitlines; and a selected wordline is biased. The bitlines are selected by selecting a first bitline in the first group and, while the first bitline is selected, selecting a second bitline in the second group which is arranged on the selected wordline symmetrically to the first bitline in the first group.

Abstract: A protective thin film coating for device packaging. A dielectric thin film coating is formed over die and package substrate surfaces prior to applying a molding compound. The protective thin film coating may reduce moisture penetration from the bulk molding compound or the interface between the molding compound and the die or substrate surfaces.