Patents Assigned to NuPGA Corporation
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Publication number: 20120094414Abstract: A method for fabricating a light-emitting integrated device, comprises overlying three layers, wherein each of the three layers emits light at a different wavelength, and wherein the overlying comprises one of: performing an atomic species implantation, performing a laser lift-off, performing an etch-back, or chemical-mechanical polishing (CMP).Type: ApplicationFiled: October 13, 2010Publication date: April 19, 2012Applicant: NuPGA CorporationInventors: Zvi Or-Bach, Deepak C. Sekar
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Publication number: 20120091474Abstract: A light-emitting integrated wafer structure, comprising: three overlying layers, wherein each of the three overlying layers emits light at a different wavelength and wherein at least one of the three overlying layers is transferred to the light-emitting integrated wafer structure using one of atomic species implants assisted cleaving, laser lift-off, etch-back, or chemical-mechanical-polishing (CMP).Type: ApplicationFiled: October 13, 2010Publication date: April 19, 2012Applicant: NuPGA CorporationInventors: Zvi Or-Bach, Deepak C. Sekar
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Publication number: 20110199116Abstract: A Configurable device comprising, a logic die connected by at least one through silicon-via (TSV), to an input/output (I/O) die.Type: ApplicationFiled: February 16, 2010Publication date: August 18, 2011Applicant: NuPGA CorporationInventors: Zvi Or-Bach, Brian Cronquist, Zeev Wurman, Israel Beinglass, J. L. de Jong
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Publication number: 20110121366Abstract: A semiconductor device includes a first single crystal silicon layer including first transistors, a first alignment mark, and at least one metal layer overlying the first single crystal silicon layer for interconnecting the first transistors; a second layer overlying the at least one metal layer, wherein the second layer includes a plurality of second transistors; and a connection path connecting the first transistors and the second transistors and including at least a first strip, a second strip, and a through via connecting the first strip and the second strip, wherein the second strip is substantially orthogonal to the first strip and wherein the through via is substantially away from both ends of the first strip and both ends of the second strip.Type: ApplicationFiled: January 28, 2011Publication date: May 26, 2011Applicant: NuPGA CorporationInventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, J.L. de Jong, Deepak C. Sekar, Paul Lim
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Publication number: 20110108888Abstract: A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.Type: ApplicationFiled: November 18, 2010Publication date: May 12, 2011Applicant: NuPGA CorporationInventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, J. L. de Jong, Deepak C. Sekar
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Publication number: 20110092030Abstract: A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.Type: ApplicationFiled: December 16, 2010Publication date: April 21, 2011Applicant: NuPGA CorporationInventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, J. L. de Jong, Deepak C. Sekar, Paul Lim
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Publication number: 20110084314Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.Type: ApplicationFiled: October 7, 2010Publication date: April 14, 2011Applicant: NuPGA CorporationInventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, J.L. de Jong, Deepak C. Sekar, Zeev Wurman
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Publication number: 20110049577Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.Type: ApplicationFiled: August 19, 2010Publication date: March 3, 2011Applicant: NuPGA CorporationInventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, J. L. de Jong, Deepak C. Sekar
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Publication number: 20110031997Abstract: A method is presented that may be used to provide a Configurable Logic device, which may be Field Programmable with volume flexibility. A method of fabricating an integrated circuit may include the steps of: providing a semiconductor substrate and forming a borderless logic array, and it may also include the step of forming a plurality of antifuse configurable interconnect circuits and/or a plurality of transistors to configure at least one antifuse. The programming transistors may be fabricated over the at least one antifuse.Type: ApplicationFiled: October 12, 2009Publication date: February 10, 2011Applicant: NuPGA CorporationInventors: Zvi Or-Bach, Brian Cronquist, Zeev Wurman, Reza Arghavani, Israel Beinglass
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Publication number: 20100295136Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.Type: ApplicationFiled: June 2, 2010Publication date: November 25, 2010Applicant: NuPGA CorporationInventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, J. L. de Jong, Deepak C. Sekar
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Publication number: 20100291749Abstract: A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.Type: ApplicationFiled: July 30, 2010Publication date: November 18, 2010Applicant: NuPGA CorporationInventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, J. L. de Jong, Deepak C. Sekar
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Publication number: 20100289064Abstract: A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layers; wherein the second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands wherein each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.Type: ApplicationFiled: August 3, 2010Publication date: November 18, 2010Applicant: NuPGA CorporationInventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, J. L. de Jong, Deepak C. Sekar