Patents Assigned to Nurlogic Design, Inc.
  • Patent number: 6617925
    Abstract: A low voltage differential signaling receiver includes a gain compensation and control circuit having a low common mode compensation circuit and a high common mode compensation circuit. A control circuit is coupled to both compensation circuits and senses the operation of one to control the operation of the other. The operation of the compensation circuits ensures that differential signals having a wide range of common mode input voltages are accurately detected by the receiver. The control circuit serves to keep the combined operation of the compensation circuits stable over the wide range of common mode input voltages.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: September 9, 2003
    Assignee: Nurlogic Design, Inc.
    Inventor: Chinh L. Hoang
  • Patent number: 6570195
    Abstract: A semiconductor device and a method of laying out the same includes routing primary power and ground distributions in the second metallization layer, rather than the first metallization as is conventionally done. This improves routability in the first metallization layer while providing sufficient current handling ability in the power and ground distributions.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: May 27, 2003
    Assignee: NurLogic Design, Inc.
    Inventors: Michael J. Brunolli, Behnan Malek-Khosravi, Nurtjahya Sambawa
  • Publication number: 20020190795
    Abstract: A low voltage differential signaling receiver includes a gain compensation and control circuit having a low common mode compensation circuit and a high common mode compensation circuit. A control circuit is coupled to both compensation circuits and senses the operation of one to control the operation of the other. The operation of the compensation circuits ensures that differential signals having a wide range of common mode input voltages are accurately detected by the receiver. The control circuit serves to keep the combined operation of the compensation circuits stable over the wide range of common mode input voltages.
    Type: Application
    Filed: June 13, 2002
    Publication date: December 19, 2002
    Applicant: Nurlogic Design, Inc.
    Inventor: Chinh L. Hoang
  • Publication number: 20020191263
    Abstract: An optical data signaling apparatus includes a trans-impedance amplifier for receiving a data signal current produced by a sensing photodiode in response to an optical data signal and an ambient current produced by a dark photodiode. Preferably, the dark photodiode has the same performance and manufacturing characteristics as the photodiode sensing the optical data signal, but is masked from receiving any light. The trans-impedance amplifier is configured to receive the ambient current from the dark photodiode as a first differential input and the data signal current from the sensing photodiode as a second differential input, the first differential input thus serving to cancel noise and environmental effects of the photodiodes, and allowing the amplifier to produce a stable and accurate differential voltage in response to the data signal current.
    Type: Application
    Filed: June 14, 2002
    Publication date: December 19, 2002
    Applicant: Nurlogic Design, Inc.
    Inventors: Chinh L. Hoang, Michael J. Brunolli
  • Publication number: 20010054720
    Abstract: A semiconductor device and a method of laying out the same includes routing primary power and ground distributions in the second metallization layer, rather than the first metallization as is conventionally done. This improves routability in the first metallization layer while providing sufficient current handling ability in the power and ground distributions.
    Type: Application
    Filed: August 13, 2001
    Publication date: December 27, 2001
    Applicant: Nurlogic Design, Inc.
    Inventors: Michael J. Brunolli, Behnan Malek-Khosravi, Nurtjahya Sambawa
  • Patent number: 6307222
    Abstract: A semiconductor device and a method of laying out the same includes routing primary power and ground distributions in the second metallization layer, rather than the first metallization as is conventionally done. This improves routability in the first metallization layer while providing sufficient current handling ability in the power and ground distributions.
    Type: Grant
    Filed: August 3, 1999
    Date of Patent: October 23, 2001
    Assignee: Nurlogic Design, Inc.
    Inventors: Michael J. Brunolli, Behnan Malek-Khosravi, Nurtjahya Sambawa
  • Patent number: 5981987
    Abstract: A semiconductor device and a method of laying out the same includes routing primary power and ground distributions in the second metallization layer, rather than the first metallization as is conventionally done. This improves routability in the first metallization layer while providing sufficient current handling ability in the power and ground distributions.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: November 9, 1999
    Assignee: Nurlogic Design, Inc.
    Inventors: Michael J. Brunolli, Behnan Malek-Khosravi, Nurtjahya Sambawa