Patents Assigned to Nuvia Inc.
  • Patent number: 11271071
    Abstract: A semiconductor device includes a substrate having a surface and a thin film inductor formed on top of the surface of the substrate and having a conductive wire, a first stack of magnetic layers and a second stack of magnetic layers. The conductive wire is disposed between the first and second stacks of magnetic layers, and the thin film inductor is configured to provide a magnetic field in the first and second stacks of magnetic layers in response to a current passing through the conductive wire. The first stack of magnetic layers has a first edge portion extending in parallel with a longitudinal axis of the conductive wire, and the second stack of magnetic layers has a second edge portion that covers the first edge portion conformally and is separated from the first edge portion by an insulation layer.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: March 8, 2022
    Assignee: Nuvia, Inc.
    Inventor: Peng Zou
  • Patent number: 10911048
    Abstract: A complementary metal-oxide semiconductor (CMOS) circuit comprises an inverter, a plurality of P-type metal-oxide semiconductor (PMOS) transistors, and a plurality of N-type metal-oxide semiconductor (NMOS) transistors. The inverter receives an input signal and drives one of the plurality of PMOS transistors or the plurality of NMOS transistors. The plurality of PMOS transistors generate a pull-up signal, change a beta ratio of the CMOS circuit, and change a first trip point of the CMOS circuit to a second trip point of the CMOS circuit based on the changed beta ratio. The plurality of NMOS transistors generate a pull-down signal, change the beta ratio, and change the second trip point of the CMOS circuit to a third trip point of the CMOS circuit based on the changed beta ratio.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: February 2, 2021
    Assignee: Nuvia Inc.
    Inventor: John Yong