Abstract: A system includes a memory and processor. The memory is configured to store a machine learning (ML) model that is trained to estimate values of frequencies added (FA) in sparse input signals that have been derived from respective input audio signals, the sparse input signals being indicative of one or more FA in the corresponding input audio signals. The processor is configured to (i) receive an input audio signal, (ii) derive from the input audio signal a sparse input signal indicative of the FA in the input audio signal, and (iii) estimate the values of the FA in the input audio signal by applying the trained ML model to the sparse input signal.

Abstract: An integrated circuit includes signal-source circuitry (SSC), an SSC power supply circuit (SSC-PS) and a digitization circuit. The SSC is configured to generate an output signal, which is guaranteed to meet specified electrical parameters provided that a supply voltage to the SSC is within a specified operating voltage range. The SSC-PS is configured to power the SSC with a reduced voltage that is below the specified operating voltage range, thereby causing the output signal to be noisy. The digitization circuit is configured to digitize the noisy output signal so as to generate a respective sequence of random numbers.

Abstract: An electronic device includes an Integrated Circuit (IC) and a package including a die-attach pad for connecting the IC. The IC includes (i) a measurement circuit configured to measure an electrical characteristic of the die-attach pad, and (ii) a security control circuit configured to initiate a responsive action responsively to detecting a deviation of the measured electrical characteristic of the die-attach pad from an initial measurement of the electrical characteristic.

Abstract: An Attack Resilient Computation Circuit (ARCC) in an integrated circuit (IC) includes a first computation stage, a second computation stage, and security circuitry. The first computation stage is configured to process one or more signals so as to produce one or more outputs, the first computation stage having multiple signal propagation paths. The second computation stage is configured to receive and process the outputs of the first computation stage. The security circuitry is configured to generate a synchronization signal indicating that propagation of the signals in the first computation stage has completed, and to inhibit the second processing stage from processing the outputs of the first processing stage for a time interval derived from the synchronization signal.

Abstract: An attack-detection (A-DET) circuit in an integrated circuit includes a main detector and a spike detection circuit. The main detector is configured to, while activated, detect an abnormal level of a power supply input of the integrated circuit. The spike detection circuit is configured to detect a transition on the power supply input and to send an activation indication to the main detector responsively the detected transition.

Abstract: An integrated circuit (IC) includes a thermal memory device, a fault injection (FI) detector and a security control circuit. The thermal memory device includes (i) a thermal storage zone and (ii) a heating element configured to heat the thermal storage zone in response to write operations. The FI detector is configured to detect attempts to inject faults into the IC. The security control circuit is configured to perform a write operation to the thermal memory device in response to an attempt detected by the FI detector, to identify a sequence of the attempts that meets a density criterion, by reading the thermal memory device, and initiate a responsive action upon identifying the sequence.

Abstract: A method includes providing one or more signals to an electronic device for performing a test procedure that involves programming a One-Time Programmable (OTP) memory in the electronic device. A verification is made as to whether connection of the one or more signals to the electronic device is stable, by performing a sequence of one or more iterations, each iteration including (i) determining, from among a set of scratchpad addresses in the OTP memory, an address that is available for programming, (ii) writing a test value to the address, and then (iii) reading the test value from the address. If the read test value differs from the written test value, re-tuning of the connection of the one or more signals is initiated. Only when the connection is verified as stable by the sequence of iterations, the OTP memory is programmed in accordance with the test procedure.

Abstract: A security device includes a memory and a processor. The memory is configured to store security firmware (FW), an active cryptographic key and an inactive cryptographic key. The active cryptographic key is associated with an active authentication certificate for authenticating the active cryptographic key, and the inactive cryptographic key is associated with an inactive authentication certificate for authenticating the inactive cryptographic key. The processor is configured to carry out security tasks by executing the security FW, and, provided a security-update indication is received, to (i) inactivate the active cryptographic key and the active authentication certificate, and (ii) activate the inactive cryptographic key and the inactive authentication certificate.

Abstract: A system includes a memory and a processor. The memory is configured to store a machine learning (ML) model. The processor is configured to (i) obtain a set of training audio signals in a form of a plurality of initial audio signals, which have first durations in a first range of durations and which are labeled with respective levels of distortion, (ii) train the ML model to estimate the levels of the distortion based on the training audio signals, (iii) receive an input audio signal having a duration in a second range of durations, shorter than the first durations, and (iv) estimate a level of the distortion in the input audio signal by applying the trained ML model to the input audio signal.

Abstract: A high order filter circuit is integrated by a plurality of the low order filter circuits. Before correcting the high order filter circuit, switch units may restore the high order filter circuit to the low order filter circuits for correction, and then combine the corrected low order filter circuits to form the original high order filter circuit.

Abstract: A low order filter circuit having a frequency correction function, a frequency correction method for a low order filter circuit, and a high order filter circuit are provided. An analog to digital converter (ADC) may detect a peak of a signal processed by a second order filter unit, and after comparison and determination are performed by a digital correction unit, a frequency control signal is outputted as a feedback to a notch filter or a band-pass filter in the second order filter unit where frequency adjustment is performed. The high order filter circuit is integrated by a plurality of the low order filter circuits. Before correcting the high order filter circuit, switch units may restore the high order filter circuit to the low order filter circuits for correction, and then combine the corrected low order filter circuits to form the original high order filter circuit.

Abstract: A processor having a core configured to control a keyboard and a plurality of pins connected to the core, configured to transfer signals from the processor to the keyboard. A controller is configured to transfer signals from one or more registers through at least one of the pins, intermittently with signals transferred to the keyboard.