Abstract: One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment.

Abstract: A method for restoring visual output to a display device. The method includes detecting a display device connection change on an output connector and changing output settings to a compatible output mode on the output connector. The method further includes cloning graphics output to the output connector. The graphics output is modified for display on the output connector. The display device is signaled to change the input source to correspond to the output connector. Subsequently, a control panel application is executed to present an on-display control for changing the output mode of the first output connector.

Abstract: One embodiment of the present invention sets forth a technique for metering a processing workload. A freeze time and run time are used to control whether or not pointers to command buffers are popped from a FIFO and the commands that generate a workload are read for processing. Smaller bursts of commands broken up by periods of idleness are coalesced by the workload metering to create larger bursts of commands during the run time and longer periods of idleness during the freeze time. Power saving features may be enabled during the periods of idleness to reduce the power consumption of the device performing the processing.

Abstract: One embodiment of the present invention sets forth a system for computing and error checking configuration parameters related to raster image generation within a graphics processing unit. Input parameters are validated by a hardware-based error checking engine. A hardware-based pre-calculation engine uses validated input parameters to compute additional private configuration parameters used by the raster image generation circuitry within a graphics processing unit.