Patents Assigned to NVIDIA Corporation
  • Patent number: 10319132
    Abstract: A method and system of representing and simulating an object by representing using with velocity-dependent particles.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: June 11, 2019
    Assignee: Nvidia Corporation
    Inventors: Tae-Yong Kim, Nuttapong Chentanez, Matthias Muller-Fischer
  • Patent number: 10319005
    Abstract: To establish a target (e.g., billing) address, a device receives a first physical address determined by geolocating the device (e.g., based on an Internet Protocol (IP) address associated with the device). A street-level map that includes an indicator that is rendered at a first location in the map corresponding to the first physical address is displayed. The indicator can be moved from the first location to one or more other locations in the map. The device receives a selection of a physical address corresponding to the location in the map of the indicator when the selection is made. The device records the selected physical address as the target address.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: June 11, 2019
    Assignee: NVIDIA Corporation
    Inventor: Andrew Fear
  • Patent number: 10319060
    Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one embodiment, the presented new approach or solution uses Operating System (OS) allocation on the central processing unit (CPU) combined with graphics processing unit (GPU) driver mappings to provide a unified virtual address (VA) across both GPU and CPU. The new approach helps ensure that a GPU VA pointer does not collide with a CPU pointer provided by OS CPU allocation (e.g., like one returned by “malloc” C runtime API, etc.).
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: June 11, 2019
    Assignee: Nvidia Corporation
    Inventors: Amit Rao, Ashish Srivastava, Yogesh Kini
  • Patent number: 10317463
    Abstract: A method for testing. The method includes sending a single instruction over a JTAG interface to a JTAG controller to select a first internal test data register of a plurality of data registers. The method includes programming the first internal test data register using the JTAG interface to configure mode control access and state control access for a test controller implementing a sequential scan architecture to test a chip at a system level.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: June 11, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Milind Sonawane, Amit Sanghani, Jonathon E. Colburn, Rajendra Kumar reddy.S, Bala Tarun Nelapatla, Sailendra Chadalavda, Shantanu Sarangi
  • Patent number: 10317459
    Abstract: A microelectronic package has an IC chip that includes logical circuitry for routing certain I/O signals to debug ports disposed on an outer surface of the microelectronic package. The I/O signals include data and command signals that are transmitted between semiconductor chips in the microelectronic package via conductive traces that are not physically accessible via with conventional debugging techniques. The logical circuitry may be configured to programmably select I/O signals based on a software input, and may be connected to the various I/O signals transmitted between the IC chip and another IC chip in the microelectronic package when a debugging of the I/O signals is enabled. Circuitry employed in conventional operation of the IC chip may also be employed to connect the logical circuitry to the various I/O signals.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: June 11, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Ish Chadha, Robert Bloemer
  • Patent number: 10317678
    Abstract: A method and system for operating a catadioptric glasses system is presented. The method includes the steps of generating an image via a light engine included in a glasses system and projecting the image onto a display that includes a diffusion layer positioned between a curved mirror and a user's retina. Light emitted from a surface of the diffusion layer is reflected off the curved mirror to the user's retina through the diffusion layer, and the diffusion layer is located between a focal point of the curved mirror and a surface of the curved mirror. The diffusion layer may be mechanically moved relative to the user's eye to enable light to pass through transparent regions in the diffusion layer in a time multiplexed fashion. The glasses system may also include a mirror stack to enable different virtual images to be formed at different depths.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: June 11, 2019
    Assignee: NVIDIA Corporation
    Inventors: Kaan Aksit, David Patrick Luebke
  • Patent number: 10311628
    Abstract: One embodiment of the present invention includes a method for rendering a geometry object in a computer-generated scene. A screen space associated with a display screen is divided into a set of regions. For each region; a first sampling factor in a horizontal dimension is computed that represents a horizontal sampling factor for pixels located in the region, a second sampling factor in a vertical dimension is computed that represents a vertical sampling factor for the pixels located in the region, a first offset in the horizontal dimension is computed that represents a horizontal position associated with the region, and a second offset in the vertical dimension is computed that represent a vertical position associated with the region. When the geometry object is determined to intersect more than one region, an instance of the geometry object is generated each region that the geometry object intersects.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 4, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Eric B. Lum, Justin Cobb
  • Patent number: 10310879
    Abstract: An embodiment of the invention sets forth a primary processing unit, a secondary processing unit coupled to the primary processing unit and accessible via a plurality of channels and a plurality of guest virtual machines executing on the primary processing unit. Each guest virtual machine includes a driver associated with the secondary processing unit, and a privileged virtual machine executing on the primary processing unit and configured to allocate a different set of channels of the plurality of channels to each of the drivers included in the guest virtual machines, where a first set of channels allocated to a first driver enables the first driver to access the secondary processing unit without conflicting with any of the other and with minimal performance overhead by directly accessing the secondary processing unit channels.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: June 4, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: William J. Earl, Kevin J. Kranzusch, Satya Kiran Popuri, Christopher W. Johnson
  • Patent number: 10312967
    Abstract: A method for transmitting data advantageously reduces cross-talk in high-speed data transmission. The method comprises receiving an input data word, encoding the input data word into a code word, and driving the code word on to an interconnect for transmission. The code word is generating using a balanced coding scheme, and the interconnect is a single-ended, twisted-wire on-chip fly-over interconnect. A receiver circuit decodes the code word to generate an output data word.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: June 4, 2019
    Assignee: NVIDIA Corporation
    Inventor: Xi Chen
  • Patent number: 10311589
    Abstract: One embodiment of the present invention sets forth a technique for estimating a head pose of a user. The technique includes acquiring depth data associated with a head of the user and initializing each particle included in a set of particles with a different candidate head pose. The technique further includes performing one or more optimization passes that include performing at least one iterative closest point (ICP) iteration for each particle and performing at least one particle swarm optimization (PSO) iteration. Each ICP iteration includes rendering the three-dimensional reference model based on the candidate head pose associated with the particle and comparing the three-dimensional reference model to the depth data. Each PSO iteration comprises updating a global best head pose associated with the set of particles and modifying at least one candidate head pose. The technique further includes modifying a shape of the three-dimensional reference model based on depth data.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: June 4, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Gregory P. Meyer, Shalini Gupta, Iuri Frosio, Nagilla Dikpal Reddy, Jan Kautz
  • Patent number: 10310973
    Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: June 4, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Nick Barrow-Williams, Brian Fahs, Jerome F. Duluk, Jr., James Leroy Deming, Timothy John Purcell, Lucien Dunning, Mark Hairgrove
  • Patent number: 10303616
    Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: May 28, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Chenghuan Jia, John Mashey, Cameron Buschardt, Sherry Cheung, James Leroy Deming, Samuel H. Duncan, Lucien Dunning, Robert George, Arvind Gopalakrishnan, Mark Hairgrove
  • Patent number: 10298422
    Abstract: A multi-stage amplifier circuit equalizes an input signal through multiple signal amplification paths. DC gain is kept substantially constant over frequency, while adjustable high-frequency gain provides equalization (e.g., peaking). Various embodiments include a common source topology, a common gate topology, differential signaling topologies, and a topology suitable for stabilizing a voltage supply against high-frequency transient loads. A system may include one or more integrated circuits that may each include one or more instances of the multi-stage amplifier.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: May 21, 2019
    Assignee: NVIDIA Corporation
    Inventors: Sanquan Song, Nikola Nedovic, John Michael Wilson, John W. Poulton, Walker Joseph Turner
  • Patent number: 10296345
    Abstract: Embodiments of the present invention are operable to communicate a list of important shaders and their current best-known compilations to remote client devices over a communications network. Client devices are allowed to produce modified shader compilations by varying optimizations. If a client device produces a modified compilation that beats an important shader's current best-known compilation, embodiments of the present invention can communicate this new best-known shader compilation back to a host computer system. Furthermore, embodiments of the present invention may periodically broadcast the new best-known shader compilation back to client devices for possible further optimization or for efficient rendering operations using the best-known shader compilation.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 21, 2019
    Assignee: Nvidia Corporation
    Inventor: Jeremy Zelsnack
  • Patent number: 10298475
    Abstract: A receiver and method for estimating an available bandwidth of a data channel streaming video data are provided. In one embodiment, the receiver includes: (1) a physical interface configured to receive the video data from a network, (2) a packet memory configured to store frames of the video data, (3) a dispersed packet time calculator configured to calculate a total time for one of the frames to go through the data channel, and (4) a bandwidth estimator configured to determine the available bandwidth of the data channel based on a number of data units received for the one frame and the total time.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: May 21, 2019
    Assignee: Nvidia Corporation
    Inventors: Reza Marandian Hagh, Thomas Meier, Alok Ahuja, Aleksandar Odorovic
  • Patent number: 10298645
    Abstract: A computer application streaming system includes an optimization unit coupled to a streaming device to determine streaming optimal playable settings for a remote user device corresponding to a selected computer application and a sending unit coupled to the optimization unit to manage streaming of the streaming optimal playable settings over a network connected to the remote user device. A receiving unit is coupled to the network to recover the streaming optimal playable settings for application to the remote user device when employing the selected computer application. An optional feedback unit is coupled to the remote user device to provide remote information over the network for modifying the streaming optimal playable settings, and an optional update unit is coupled to the streaming device to manage modification of the streaming optimal playable settings as directed by the remote information. A method of streaming a computer application is also provided.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: May 21, 2019
    Assignee: Nvidia Corporation
    Inventors: John Spitzer, Hassane Azar, Alok Ahuja, Tony Tamasi
  • Patent number: 10289418
    Abstract: Techniques are provided for handling a trap encountered in a thread that is part of a thread array that is being executed in a plurality of execution units. In these techniques, a data structure with an identifier associated with the thread is updated to indicate that the trap occurred during the execution of the thread array. Also in these techniques, the execution units execute a trap handling routine that includes a context switch. The execution units perform this context switch for at least one of the execution units as part of the trap handling routine while allowing the remaining execution units to exit the trap handling routine before the context switch. One advantage of the disclosed techniques is that the trap handling routine operates efficiently in parallel processors.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 14, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Gerald F. Luiz, Philip Alexander Cuadra, Luke Durant, Shirish Gadre, Robert Ohannessian, Lacky V. Shah, Nicholas Wang, Arthur Danskin
  • Patent number: 10289469
    Abstract: Systems and methods for enhancing reliability are presented. In one embodiment, a system comprises a processor configured to execute program instructions and contemporaneously perform reliability enhancement operations (e.g., fault checking, error mitigation, etc.) incident to executing the program instructions. The fault checking can include: identifying functionality of a particular portion of the program instructions; speculatively executing multiple sets of operations contemporaneously; and comparing execution results from the multiple sets of operations. The multiple sets of operations are functional duplicates of the particular portion of the program instructions. If the execution results have a matching value, then the value can be made architecturally visible. If the execution results do not have a matching value, the system can be put in a safe mode. An error mitigation operation can be performed can include a corrective procedure. The corrective procedure can include rollback to a known valid state.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 14, 2019
    Assignee: Nvidia Corporation
    Inventors: Nick Fortino, Fred Gruner, Ben Hertzberg
  • Publication number: 20190138821
    Abstract: System and methods for detecting blockages in images are described. A method may include receiving a plurality of images captured by a camera installed on a vehicle. The method may include identifying one or more candidate blocked regions in the plurality of images. Each of the candidate blocked regions may contain image data caused by blockages in the camera's field-of-view. The method may further include assigning blockage scores to the one or more candidate blocked regions based on region-associations among the one or more candidate blocked regions in the plurality of images. In response to a determination that one of the blockage scores is above a predetermined blockage threshold, the method may include transmitting a blockage alarm signal to the vehicle.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 9, 2019
    Applicant: NVIDIA CORPORATION
    Inventors: Xiaoyan MU, Xiaohan HU
  • Patent number: 10284269
    Abstract: A communications system has a cellular structure including a base station that is located within a cell of the cellular structure and provides an elevation beamforming transmission based on a set of elevation precoding matrix indicator offsets in an elevation codebook. The communications system also includes user equipment that is located within the cell and coupled to the base station to receive the set of elevation precoding matrix indicator offsets and a set of reference signals to provide channel quality and inter-cell interference measurements, wherein a selected channel quality indicator is based on an increase in channel quality with respect to inter-cell interference at the user equipment and corresponds to one of the set of elevation precoding matrix indicator offsets. A method of operating a communications system having a cellular structure is also provided.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: May 7, 2019
    Assignee: Nvidia Corporation
    Inventors: Pekka Janis, Tommi Koivisto, Kari Hamalainen