Abstract: Method, receiver and computer program product for processing a signal transmitted over a wireless network from a plurality of spatially separated transmit antennas of a transmitter using a Multiple-Input Multiple-Output transmission. The signal is received at a plurality of receive antennas, the signal comprising a plurality of data streams. The channel quality for each of the data streams in the received signal is determined and based on the determined channel quality of the data streams, the number of independent data streams that can be supported in the Multiple-Input Multiple-Output transmission of the signal is determined. An indication of the determined number is transmitted to the transmitter.

Abstract: According to embodiments disclosed herein, there is disclosed a computer processor architecture; and in particular a computer processor, a method of operating the same, and a computer program product that makes use of an instruction set for the computer. In one embodiment, the computer processor includes: (1) a decode unit for decoding instruction packets fetched from a memory holding the instruction packets, (2) a control processing channel capable of performing control operations and (3) a data processing channel capable of performing data processing operations, wherein, in use the decode unit causes instructions of instruction packets comprising a plurality of only control instructions to be executed sequentially on the control processing channel, and wherein, in use the decode unit causes instructions of instruction packets comprising a plurality of instructions comprising at least one data processing instruction to be executed simultaneously on the data processing channel.

Abstract: A device comprises a processor arranged to automatically execute boot code upon start-up or reset. The boot code comprises a code authentication procedure to verify whether additional code is authenticated for execution on the processor. A separate security unit comprises a private unlock key and cryptography logic configured to use the private unlock key to sign a portion of data, thereby generating a signed unlock file for supply to a storage location. The processor is arranged to access the unlock file from the storage location, making it available without requiring connection to the security unit. The boot code further comprises an unlocking authentication procedure configured to check for the unlock file in the storage location, and if available to verify whether the unlock file is authenticated for use on the processor based on its signature, so as to de-restrict the boot authentication procedure on condition of verifying the unlock file.

Abstract: Method and apparatus for processing a signal using a recursive method for determining a plurality of frequency components of the signal, the signal being a chirp-like polyphase sequence, wherein a first frequency component of the plurality of frequency components is determined; a component factor is determined by accessing a factor table for use in determining a second frequency component of the plurality of frequency components; and the second frequency component is determined using the determined first frequency component and the determined component factor.

Abstract: Method and computing system for controlling a supply voltage in the computing system. A voltage related indication for use in setting the supply voltage of the computing system is stored, and a supply voltage is set for the computing system based on the stored voltage related indication. A crash of the computing system is detected, and in dependence thereon, an adjusted indication is determined for use in the computing system. An adjusted supply voltage is set based on the adjusted indication, and the adjusted indication is stored for further use of the computing system.

Abstract: A method, device and computer program product is provided for sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device, the radio frequency circuit being configured for at least one of transmission and reception of radio signals in a radio frequency band, where the clock signal has a clock frequency Fc. The method comprises selecting the clock frequency Fc to be a rational multiple of the 0.270833 MHz symbol rate of the Global System for Mobile Communications (GSM) standard and a rational multiple of the 3.84 MHz chipping rate of the Wideband Code Division Multiple Access (WCDMA) interface. The clock frequency Fc is selected such that the clock signal can be generated using a 38.4 MHz or 19.2 MHz reference clock signal, a non-fractional Phase Locked Loop clock multiplier and an output divider, without first having to divide down the reference clock signal.

Abstract: Method, receiver and computer program product for processing a signal, wherein the signal is received over a wireless network from a transmitter, the signal comprising a plurality of data streams. A selected one of the data streams is preferentially treated by reporting an adjusted value of a characteristic of the selected data stream to the transmitter and the received signal is decoded using a technique of successively decoding data streams in which the selected data stream is the first data stream to be decoded, a signal corresponding to the selected data stream being removed from the received signal prior to decoding at least one of the unselected data streams in the received signal.

Abstract: A method, program and user equipment for wireless communication in a cellular communication system comprising a plurality of base stations. The method comprises: synchronizing to one of said the base stations using a synchronization channel transmitted from that base station; receiving a pilot channel from said base station; after synchronizing to said base station, receiving a signal from that base station; and using the pilot channel from said base station to cancel interference on said signal caused by the synchronization channel.

Abstract: A method of sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device. The method comprises: determining whether at least one of the data signal and the clock signal is disturbing in that it has a harmonic within the radio frequency band. If it is determined that at least one of the data signal and the clock signal is disturbing, the method further comprises: scrambling the at least one disturbing signal to flatten the spectrum thereof for frequencies below the clock frequency FC, setting a respective at least one indicator to indicate that the at least one disturbing signal has been scrambled, and sending the at least one scrambled signal between the radio frequency circuit and the baseband circuit. The method further comprises, subsequent to the step of sending the at least one scrambled signal, descrambling the at least one scrambled signal if the respective at least one indicator is set.

Abstract: A circuit for multiplying a digital signal by a variable gain, controlled in dependence on a digital gain control value. The circuit comprises: a multiplier input for receiving the digital signal; a multiplier output for outputting the digital signal multiplied by the gain; a plurality of multiplier stages each arranged to multiply by a respective predetermined multiplication factor; and switching circuitry arranged so as to apply selected ones of the multiplier stages in a multiplication path between the input and output, in dependence on the digital gain control value. The multiplication factors are arranged such that binary steps in the digital gain control value result in logarithmic steps in said gain.

Abstract: Integrated circuit and method for generating a clock signal, the integrated circuit comprising (i) a frequency locked loop comprising a voltage controlled oscillator configured to receive a control input and to generate a clock signal determined by the control input; and (ii) a microprocessor configured to be powered by a supply voltage and to receive the clock signal generated by the voltage controlled oscillator. The integrated circuit is configured to use the supply voltage as the control input, such that the clock signal is determined by the supply voltage.

Abstract: A method, device and computer program product is provided for sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device, the radio frequency circuit being configured for at least one of transmission and reception of radio signals in a radio frequency band, where the clock signal has a clock frequency Fc. The method comprises selecting the clock frequency Fc to be a rational multiple of the 0.270833 MHz symbol rate of the Global System for Mobile Communications (GSM) standard and a rational multiple of the 3.84 MHz chipping rate of the Wideband Code Division Multiple Access (WCDMA) interface. The clock frequency Fc is selected such that the clock signal can be generated using a 38.4 MHz or 19.2 MHz reference clock signal, a non-fractional Phase Locked Loop clock multiplier and an output divider, without first having to divide down the reference clock signal.

Abstract: Method, receiver and computer program product for processing a signal transmitted from a plurality of spatially separated transmit antennas using a Multiple-Input Multiple-Output transmission over a wireless network. The signal is received at a plurality of spatially separated receive antennas, the signal comprising a plurality of data streams and the quality/reliability of each of the data streams in the received signal is determined. Based on the determined quality/reliability of the data streams, a decoding technique is selected to be one of (i) a successive decoding technique for successively decoding data streams in which one of the data streams is decoded and a signal corresponding to said one of the data streams is removed from the received signal prior to decoding further data streams in the received signal, and (ii) a non-successive decoding technique in which each data stream is decoded from the received signal by treating the other data streams as noise in the received signal.

Abstract: Method, receiver and computer program product for processing a signal transmitted from a plurality of spatially separated transmit antennas using a Multiple-Input Multiple-Output transmission over a wireless network. The signal is received at a plurality of spatially separated receive antennas, the signal comprising a plurality of data streams and the quality/reliability of each of the data streams in the received signal is determined. Based on the determined quality/reliability of the data streams, a decoding technique is selected to be one of (i) a successive decoding technique for successively decoding data streams in which one of the data streams is decoded and a signal corresponding to said one of the data streams is removed from the received signal prior to decoding further data streams in the received signal, and (ii) a non-successive decoding technique in which each data stream is decoded from the received signal by treating the other data streams as noise in the received signal.

Abstract: Method, receiver and computer program product for processing a signal transmitted over a wireless network from a plurality of spatially separated transmit antennas of a transmitter using a Multiple-Input Multiple-Output transmission. The signal is received at a plurality of receive antennas, the signal comprising a plurality of data streams. The channel quality for each of the data streams in the received signal is determined and based on the determined channel quality of the data streams, the number of independent data streams that can be supported in the Multiple-Input Multiple-Output transmission of the signal is determined. An indication of the determined number is transmitted to the transmitter.

Abstract: Method and apparatus for processing a signal using a recursive method for determining a plurality of frequency components of the signal, the signal being a chirp-like polyphase sequence, wherein a first frequency component of the plurality of frequency components is determined; a component factor is determined by accessing a factor table for use in determining a second frequency component of the plurality of frequency components; and the second frequency component is determined using the determined first frequency component and the determined component factor.

Abstract: Method, receiver and computer program product for processing a signal, wherein the signal is received over a wireless network from a transmitter, the signal comprising a plurality of data streams. A selected one of the data streams is preferentially treated by reporting an adjusted value of a characteristic of the selected data stream to the transmitter and the received signal is decoded using a technique of successively decoding data streams in which the selected data stream is the first data stream to be decoded, a signal corresponding to the selected data stream being removed from the received signal prior to decoding at least one of the unselected data streams in the received signal.

Abstract: A method of sending a data signal and a Downlink Uplink clock signal between a radio frequency circuit of a device and a baseband circuit of the device. The method comprises: determining whether at least one of the data signal and the clock signal is disturbing in that it has a harmonic within the radio frequency band. If it is determined that at least one of the data signal and the clock signal is disturbing, the method further comprises: scrambling the at least one disturbing signal to flatten the spectrum thereof for frequencies below the clock frequency FC, setting a respective at least one indicator to indicate that the at least one disturbing signal has been scrambled, and sending the at least one scrambled signal between the radio frequency circuit and the baseband circuit. The method further comprises, subsequent to the step of sending the at least one scrambled signal, descrambling the at least one scrambled signal if the respective at least one indicator is set.

Abstract: Integrated circuit and method for generating a clock signal, the integrated circuit comprising (i) a frequency locked loop comprising a voltage controlled oscillator configured to receive a control input and to generate a clock signal determined by the control input; and (ii) a microprocessor configured to be powered by a supply voltage and to receive the clock signal generated by the voltage controlled oscillator. The integrated circuit is configured to use the supply voltage as the control input, such that the clock signal is determined by the supply voltage.

Abstract: Method and computing system for controlling a supply voltage in the computing system. A voltage related indication for use in setting the supply voltage of the computing system is stored, and a supply voltage is set for the computing system based on the stored voltage related indication. A crash of the computing system is detected, and in dependence thereon, an adjusted indication is determined for use in the computing system. An adjusted supply voltage is set based on the adjusted indication, and the adjusted indication is stored for further use of the computing system.