Abstract: Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and control logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a read inline encryption engine (IEE) connected to the memory interface, wherein the read IEE is configured to decrypt encrypted data read from the memory; a key selector configured to determine a read memory region associated with the memory read request based upon a read address where the data to be read is stored, wherein the read address is received from the address and control logic; and a key logic configured to select a first key associated with the determined read memory region and provide the selected key to the read IEE.

Abstract: A signal processing IC unit performs image processing with respect to an output from a camera. A recognition processing IC unit performs recognition processing based on the output from the signal processing IC unit. A control IC unit outputs a control signal based on the output from the recognition processing IC unit. A first terminal is electrically connected to the recognition processing IC unit. A second terminal is electrically connected to the control IC unit. The signal processing IC unit, the recognition processing IC unit, and the control IC unit are disposed on a board. The first terminal and the second terminal are provided on an edge portion of the board.

Abstract: A mechanism is provided to reduce interference between vehicular radar systems through communicating radar parameters and physical orientation between vehicles and then using directional information to form clusters of radars, which will have consistent modulation parameters. Radar modulation parameters, such as starting frequency, center frequency, bandwidth, slope, ramp direction, timing, and the like for frequency-modulated continuous-wave (FMCW) radars, are adjusted to reduce or eliminate inter-cluster direct interference between clusters oriented in different directions. For other types of radars, in some embodiments, other operational parameters can be adjusted. In some embodiments, some modulation parameters also can be adjusted to reduce or eliminate intra-cluster indirect interference.

Abstract: A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.

Abstract: A method for power management for applications having duty-cycled high peak supply currents includes charging a buffer capacitor with a first current supplied by a battery, wherein the first current is limited by a current limiter. A load is supplied with a second current supplied by the buffer capacitor, wherein the second current comprises a pulsed current. The current limiter is controlled with at least one of a plurality of sensor inputs to limit a capacity degradation of the battery.

Abstract: Embodiments combine error correction code (ECC) and transparent memory built-in self-test (TMBIST) for memory fault detection and correction. An ECC encoder receives input data and provides ECC data for data words stored in memory. Input XOR circuits receive the input data and output XOR'ed data as payload data for the data words. Output XOR circuits receive the payload data and output XOR'ed data. An ECC decoder receives the ECC data and the XOR'ed output data and generates error messages. Either test data from a controller running a TMBIST process or application data from a processor executing an application is selected as the input data. Either test address/control signals from the controller or application address/control signals from the processor are selected for memory access. During active operation of the application, memory access is provided to the processor and the controller, and the memory is tested during the active operation.

Abstract: A Radio Frequency Identification (RFID) tag is disclosed. The RFID tag includes an antenna port to receive an input AC signal and a hybrid limiter including a clamping device configured to limit a voltage of the input AC signal to a preconfigured limit. The hybrid limiter is configured to provide a stable ground reference for the clamping device.

Abstract: Aspects of the present disclosure may involve use of a radio frequency receiver and in such a receiver, tracking multipath gains and delays of multipath reflections corresponding to an OFDM multipath transmission channel. The gains and delays are based on time-domain evolution of the channel impulse response. Multipath reflections are searched for and then used to calculate channel correlation information to provide channel estimations to aid in mitigating or cancelling distortion of the received signal.

Abstract: One example discloses a reconfigurable analog to digital converter (ADC) device, including: an analog front end (AFE) configured to receive a set of analog input signals and generate a corresponding set of digital output signals; wherein the AFE includes a set of reconfigurable ADC conversion circuits; and a sequencer coupled to the AFE and configured to control the set of reconfigurable ADC conversion circuits with a first AFE channel configuration at a first time and a second AFE channel configuration at a second time.

Abstract: Example aspects are directed to operating a SPAD receiver such as may be used in a light detection and ranging (Lidar) system. In one example, the SPAD receiver has SPAD circuitry for multiple photon detections using a single-channel TDC (time-to-digital converter), and such photon detection is quenched after detection so as to establish an effective pre-defined OFF period. In response, the SPAD circuitry is recharged for a subsequent ON period during which the SPAD circuitry is unquenched (or armed) for further photon detection and processing.

Abstract: Embodiments of an SMPS controller and a method for operating a switched-mode power supply (SMPS) controller are described. In an embodiment, an SMPS controller includes a gate driver circuit configured to generate a drive signal for a switch of an SMPS and a current sense electrical terminal configured to receive sensed current corresponding to the switch and to conduct driver discharge current from the gate driver circuit.

Abstract: One example discloses a near-field wireless communications device, including: a near-field antenna; a near-field noise detector coupled to receive a first set of near-field signals from the near-field antenna; wherein the near-field noise detector is configured to identify a set of attributes of the near-field noise within the first set of near-field signals; a controller configured to generate at least one synchronization signal based on at least one of the attributes of the near-field noise; and a transmitter circuit configured to transmit a second set of near-field signals in response to the synchronization signal.

Abstract: An access control system controls access to a shared resource for various functional circuits. The access control system can include a comparison circuit, a processing circuit, and a selection circuit. The comparison circuit receives identification data associated with a functional circuit based on a transaction initiated by the functional circuit, and compares the identification data and reference data to generate a select signal. The processing circuit receives error data and response data outputted by the shared resource based on an execution of the transaction, and generates another response data. The selection circuit selects and outputs, based on the select signal, one of the response data outputted by the shared resource and the response data generated by the processing circuit as a transaction response that is to be provided to the functional circuit.

Abstract: A lockstep testing system includes a lockstep controller that generates various control signals. The lockstep testing system further includes various lockstep circuitries, with each lockstep circuitry including primary and redundant functional circuits that are operable in a lockstep mode, and a fault injection circuit that receives a control signal from the lockstep controller and injects a transient fault in the corresponding lockstep circuitry. The transient fault can be injected at one of input and output stages of the primary and redundant functional circuits. Each lockstep circuitry further includes a checker circuit that tests whether the corresponding lockstep circuitry is faulty (i.e., whether the injected fault is accurately detected), and generates and provides, to the lockstep controller, a fault indication signal indicating whether the corresponding lockstep circuitry is faulty.

Abstract: A radar system is disclosed that provides joint object detection and communication capabilities. The radar system includes a communication signal generator that provides a communication signal, a pre-distortion module that applies a pre-distortion to the communication signal to provide a pre-distorted communication signal, a linear frequency modulation (LFM) signal generator that provides a LFM signal, and a mixer that mixes the pre-distorted communication signal onto the LFM signal to provide a radar signal to be transmitted by the radar system. The radar system further includes an all-pass filter that filters a plurality of de-ramped reflected images of the radar signal to provide a filtered signal. Each de-ramped reflected image includes an associated image of the pre-distorted communication signal. The all-pass filter provides a linear group delay, and a non-linear phase response. The pre-distortion is an inverse of the non-linear phase response of the all-pass filter.

Abstract: Embodiments address the problem of detecting anomalies in data sets with respect to well-defined normal behavior. Deviations of data collected in real-time are detected using a previously observed distribution of data known to be benign. Embodiments provide techniques to detect varying types of anomalies by creating multiple aggregation layers having varying granularities on top of the lowest level of data collection. This allows detection of fine anomalies that strongly impact single data points, as well as coarse anomalies that detect multiple data points less strongly. Machine learning models are trained and used to compare real-time data sets against behavior of a benign data set in order to detect differences and to flag anomalous behavior.

Abstract: A method for first path acceptance for secure ranging includes determining a Channel Impulse Response (CIR) of a communication channel for a plurality of channel taps. Each channel tap corresponds to a respective one of a plurality of time slots of the CIR, wherein the CIR includes a plurality of estimated CIR values. A statistical characteristic is extracted from the estimated CIR values within a temporal range of the channel taps. The statistical characteristic is compared to a reference value to detect a distance decreasing attack.

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (??LO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.

Abstract: A switched capacitor (SC) power stage includes a first stage circuit with a set of switches coupled in series, a first flying capacitor coupled to a first node between a first and second switch and to a second node between a fifth and sixth switch, a second flying capacitor coupled to a third node between the second and a third switch and to a fourth node between a seventh and eighth switch, and a third flying capacitor coupled to a fifth node between a third and fourth switch and a second terminal coupled to the second node. A control circuit establishes a first configuration of the switches to precharge the first, second, and third flying capacitors to a first voltage, and a second configuration of the switches to precharge the first and second flying capacitors to a second voltage while the third flying capacitor remains charged at the first voltage.

Abstract: An integrated circuit (IC) includes an input/output (I/O) circuitry with a first circuitry section including I/O pins and a second circuitry section including I/O pins. The first and second circuitry sections are mutually exclusive sections of the I/O ring. The first circuitry section includes a first I/O pin configured to receive an input voltage from a first energy source and a second I/O pin connectable to an external startup capacitor. A startup circuit is coupled to the first I/O pin and the second I/O pin. Upon receiving the input voltage from the first energy source, the startup circuit enters a during the startup phase and isolates the first circuitry section from the second circuitry section, and provides charge to the external startup capacitor. In response to achieving a predetermined minimum charge on the external startup capacitor, the first circuitry section is connected to the second circuitry section, and the startup phase ends and the IC transitions to a functional mode of operation.