Abstract: A memory cell structure includes non-volatile as well as SRAM memory cells that share the same bitline and operate differentially. The SRAM cell includes first and second MOS transistors that are coupled to the same true and complementary bit lines that the non-volatile memory cells are coupled to. The non-volatile memory cells are erased prior to being programmed. Programming of the non-volatile memory cells may be carried out via hot-electron injection or Fowler-Nordheim tunneling. Data stored in the non-volatile memory cells may be transferred to the SRAM cell. The differential reading and writing of data reduces over-erase of the non-volatile devices.