Abstract: A communication system is provided for interconnecting a network of digital systems. Each node of the communication system may include a transceiver and an encoder/decoder. The encoder codes an incoming data stream and forwards the encoded data stream across a communication link based on a DC-adaptive encoding mechanism. The encoded data stream is substantially free of a DC value that would skew the detector components at the receiver end of the communication link. Moreover, the encoded signal is forwarded at no greater than the incoming bitstream. Encoding occurs dependent on a digital sum value of the preceding clock cycle (DSVn−1) for the encoded bitstream and the logic values for the incoming bitstream during the current clock cycle n as well as the subsequent clock cycle n+1. Encoding according to normal encoding or multiple-ones encoding is dependent on those values.

Abstract: An apparatus and method for clocking digital and analog circuits on a common substrate is provided. The apparatus and method serves to reduce digitally derived noise at select times during which the analog input signal is sampled. Analog sampling error is thereby reduced while, at the same time, the digital clocking signal maintains maximum frequency. Digitally derived noise is substantially eliminated near the latter portion of each sampling interval to ensure an accurate sampled value exists at the culmination of that interval. During the earlier portion of each sampling interval, digital clocking pulses are maintained at a high frequency so as to enhance processing speeds. It is determined that only the latter portion of each sample interval is critical to the reduction of sampling error. Furthermore, the digital clocking pulses occur a non-power-of-two factor to ensure tonal noise is not coupled into the analog circuit frequency band of interest.

Abstract: An apparatus is provided for automatically and dynamically adjusting a frequency division factor of a clock divider situated in the feedback loop of a phase-locked loop (PLL). The frequency division factor is modified based on changes in the input signal frequency forwarded to the PLL. If the input signal frequency increases, the decision circuit coupled to the input of the voltage controlled oscillator records that change as an encoded digital signal. That signal will accordingly modify the current frequency division factor dependent on current division factor as well as the current input signal frequency. The decision circuit can be modeled as an A/D converter, and the control unit placed between the decision circuit and the clock divider can be modeled as a state diagram. Each state of the state diagram is indicative of a frequency division factor, or a change in that division factor, wherein the coded digital signal indicates possible change from one state to another.

Abstract: A circuit is provided for controlling or regulating a phase-locked loop (PLL) output during times when the PLL is unlocked. Noise or corruption on the input signal of the PLL may cause the PLL output frequency to suddenly rise to match the input signal frequency. In many instances, the noise or corruption cannot be filtered by the low pass filter within the PLL. A detection circuit is coupled to receive the input signal, and discern times in which non-filterable noise occurs. The detection circuit may include a decoder which decodes, e.g., error correction coding within the input signal data stream to indicate possible instances in which the PLL will unlock. Once the detection circuit indicates an unlock condition and forwards an unlock selection signal to a multiplexer, the multiplexer chooses a frequency divided clocking signal rather than the PLL output clocking signal.

Abstract: A digital filter is provided for achieving substantial attenuation of aliasing or imaging bands of a signal to be filtered. The digital filter employs a comb filter technique, wherein the comb filter can perform decimation or interpolation, depending upon its application. The comb filter is a multi-stage element, having more than one stage, and having an overall word length, W.sub.L, optimally reduced. The total number of terms within the cumulative set of stages is also optimally reduced. The comb decimation or interpolation filter architecture is therefore of minimum size if employed in hardware, or utilizes minimal operations if employed in software. A filter element within the comb decimation or interpolation filter includes a z-transform C.sub.K (Z) term. The filter element can be reduced to a simple z-transform 1+z.sup.-1 term if the stage of interest includes a decimate-by-two or interpolate-by-two rate change switch.

Abstract: Two embodiments of a digital signal processor are described. Each embodiment is configured with an instruction processing pipeline including an execute-write pipeline stage. When an instruction reaches the execute-write pipeline stage, the instruction is executed and the corresponding result is written to the specified destination. Additionally, the execute-write stage maintains a relatively short pipeline. One embodiment described herein employs an instruction set in which the destination of an instruction may be encoded within a subsequent instruction. The number of bits utilized to encode a particular instruction is reduced by the number of bits that would have specified the destination.

Abstract: A D/A switched capacitor circuit, employed as part of a delta-sigma modulator, is provided. The modulator forms part of an A/D converter system, and the switched capacitor circuit is controlled by careful selection of clock phases. The clock phases, or more specifically four clock phases, are provided to ground both plates of switched capacitors within the D/A circuit subsequent to their discharge upon the integrator and prior to the next sampling period. Full discharge of shared capacitors to a ground voltage substantially eliminates any data dependent loading of integrator offset voltages upon the reference voltage supplies. Substantial reduction or elimination of data-dependent values prevents ac modulation of the referenced voltage supply and the imputed noise associated therewith.

Abstract: A modulator, in conjunction with a load circuit, is provided. The modulator forms part of an A/D converter system. The modulator includes a series of switched capacitors connected in a shared capacitor arrangement. The shared capacitors receive samples from an input signal and, depending upon the logic value fed into a D/A converter, the shared capacitor further receives a feedback reference voltage. The reference voltage is thereby coupled to the switched capacitor network, as well as to a load circuit which cancels data-dependent values modulated upon the reference voltage supply. The load circuit thereby serves to eliminate ac components within the reference voltage supply resulting from data dependent loading.

Abstract: An analog-to-digital (A/D) converter is provided for converting an analog signal to a digital signal, wherein the digital signal is corrected such that it does not contain DC offset. The A/D converter preferably comprises a delta-sigma modulator and an offset compensation circuit. The offset compensation circuit is coupled to the output of the modulator or, according to another embodiment, to the output of a noise cancellation circuit. The offset compensation circuit can calibrate a single bit output from the modulator or a multi-bit output from the noise cancellation logic. In the former instance, the offset compensation circuit includes an up/down counter and register; in the latter instance, the calibration circuit includes an accumulator. The offset compensation circuit counts or accumulates a digital representation of DC offset.