Abstract: One may use a new technique to determine the placement of exclusive-ors in each scan string of a chip to achieve improved test vector compression, and one may combine this technique with methods to minimize the overhead of the exclusive-or logic, to eliminate clock enable logic for multiple scan strings, to minimize the changes to existing test logic insertion and scan string reordering, and to minimize the test vector compression computation time.
Abstract: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.
Abstract: One may use a new technique to determine the placement of exclusive-ors in each scan string of a chip may achieve improved test vector compression, and one may combine this technique with methods to minimize the overhead of the exclusive-or logic, to eliminate clock enable logic for multiple scan strings, to minimize the changes to existing test logic insertion and scan strings reordering, and to minimize the test vector compression computation time.