Abstract: Architectures and methods for performing big data analytics by providing an integrated storage/processing system containing non-volatile memory devices that form a large, non-volatile memory array and a graphics processing unit (GPU) configured for general purpose (GPGPU) computing. The non-volatile memory array is directly functionally coupled (local) with the GPU and optionally mounted on the same board (on-board) as the GPU.

Abstract: Computer systems and methods that utilize a GPU whose operation is able to switch between ECC and non-ECC memory operations on demand. The computer system includes a graphics processing unit and a memory controller and local memory that are functionally integrated with the graphics processing unit. The memory controller has at least two operating modes comprising a first memory access mode that uses error checking and correction when accessing the local memory, and a second memory access mode that does not use error checking and correction when accessing the local memory. The memory controller is further operable to switch the operation of the memory controller between the first and second memory access modes without rebooting the computer system.

Abstract: A PCIe bus extension system, method, interface card and cable for connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system. The interface card includes a printed circuit board, an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the interface card, an interface port configured to mate with a connector of the cable, and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the expansion slot and amplifying and propagating clock and data PCIe signals therebetween that are compliant with a PCIe standard. The interface card and cable lacks the capability of transmitting power therethrough to a PCIe-compliant peripheral device connected to the interface card through the interface port.

Abstract: A non-volatile solid state memory-based mass storage device having at least one non-volatile memory component and methods of operating the storage device. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.

Abstract: A controller for a solid state disk is provided. The controller includes a storage module to store an index of at least one idle bank among a plurality of memory banks, and a control module to control an access to the at least one idle bank using the stored index. Here, the access to the at least one idle bank may be controlled based on a state of a channel corresponding to each of the at least one idle bank.

Abstract: A memory system and method for generating and transferring parity information within burst transactions of burst read and write transfers and without dedicated parity chips or parity data lines.

Abstract: Disclosed is a flash memory controlling method and controlling device. The flash memory controlling method including calculating a cost for each of available block recycling schemes based on a multi-block erase function when the multi-block erase function is supported, the multi-block erase function being a function that simultaneously erases data stored in a plurality of blocks of a flash memory and selecting at least one scheme from among the available block recycling schemes based on the calculated cost, and managing at least one block using the at least one method selected from among the available block recycling schemes.

Abstract: A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed circuit board, a system expansion slot interface on the printed circuit board and comprising power and data pins, a host bus controller on the printed circuit board and electrically connected to the system expansion slot interface, docking connectors connected with the host bus controller to receive power and exchange data therewith and adapted to electrically couple with industry-standard non-volatile memory devices without cabling therebetween, and features on the printed circuit board for securing the memory devices thereto once coupled to the docking connectors.

Abstract: A NAND flash memory device and method of erasing memory cells thereof, wherein each cell is only subjected to the level of erase voltage needed to restore its nominal “erased” state. Each memory cell of the NAND flash memory device comprises a floating gate, a control gate connected to a wordline and receives a control voltage therefrom to induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge. Each memory cell further includes circuitry for modulating the erase voltage according to the level of the programming charge on its floating gate.

Abstract: A solid state drive that uses over-provisioning of NAND flash memory blocks as part of housekeeping functionality, including deduplication and coalescence of data for efficient usage of NAND flash memory devices and maintaining sufficient numbers of erased blocks to promote write performance.

Abstract: A solid-state mass storage device and method of operating the storage device to anticipate the failure of at least one memory device thereof before a write endurance limitation is reached. The method includes assigning at least a first memory block of the memory device as a wear indicator that is excluded from use as data storage, using pages of at least a set of memory blocks of the memory device for data storage, writing data to and erasing data from each memory block of the set in program/erase (P/E) cycles, performing wear leveling on the set of memory blocks, subjecting the wear indicator to more P/E cycles than the set of memory blocks, performing integrity checks of the wear indicator and monitoring its bit error rate, and taking corrective action if the bit error rate increases.

Abstract: A mass storage device that utilizes one or more solid-state memory components to store data for a host system, and a method for increasing the write endurance of the memory components. The memory components are periodically heated above an intrinsic operating temperature thereof to a preselected temperature that is sufficient to thermally recondition the memory component in a manner that increases the write endurance of the memory component.

Abstract: A solid-state mass storage device and method of anticipating a failure of the mass storage device resulting from a memory device of the mass storage device reaching a write endurance limit. A procedure is then initiated to back up data to a second mass storage device prior to failure. The method includes assigning at least a first memory block of the memory device as a wear indicator, using other memory blocks of the memory device as data blocks for data storage, performing program/erase (P/E) cycles and wear leveling on the data blocks, subjecting the wear indicator to more P/E cycles than the data blocks, performing integrity checks and monitoring the bit error rate of the wear indicator, and taking corrective action if the bit error rate increases, including the initiation of the backup procedure and generating a request to replace the device.

Abstract: Non-volatile storage devices and methods capable of achieving large capacity solid state drives containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and a memory controller. The bank switching circuitry is integrated onto the memory controller and functionally interposed between the banks of memory devices and the front end of the memory controller. The bank switching circuitry operates to switch accesses by the memory controller among the at least two banks.

Abstract: A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed circuit board, a system expansion slot interface on the printed circuit board and comprising power and data pins, a host bus controller on the printed circuit board and electrically connected to the system expansion slot interface, docking connectors connected with the host bus controller to receive power and exchange data therewith and adapted to electrically couple with industry-standard non-volatile memory devices without cabling therebetween, and features on the printed circuit board for securing the memory devices thereto once coupled to the docking connectors.

Abstract: A system and method for increasing DDR memory bandwidth in DDR SDRAM modules are provided. DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued on CAS latency before the completion of the ongoing data burst and the effect of the CAS latency is minimized in terms of the effect on bandwidth. The system and method optimizes the remaining two access latencies (tRP and tRCD) for optimal bandwidth.

Abstract: A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode but instead used to shuffle data within the at least one block using a dynamic page address scheme, whereby data are dynamically moved from one page to an empty page in the same block using dynamic page mapping.

Abstract: A solid-state mass storage device and method for its operation that includes performing preemptive scrubbing of data during offline periods or disconnects from a host system to which the mass storage device is attached. The device includes a system interface adapted to connect the drive to a host system, at least one nonvolatile memory device, controller means through which data pass when being written to and read from the memory device, a volatile memory cache, a system logic device, and an integrated power source for powering the drive. The system logic device is configured to operate when the drive is not functionally connected to a host system, execute copy commands without accessing a host system, and prioritize preemptive scrubbing of addresses in the memory device on the basis of risk of data loss based on one or more parameters logged by the internal system logic device.

Abstract: A nonvolatile memory device and method using phase changes in a substrate to alter optical properties of the substrate for the purpose of data storage. The memory device includes a substrate containing a phase change material having phases comprising amorphous and crystalline phases. The phase change material has optical properties that change depending on whether the phase change material is in the amorphous phase or the crystalline phase. The memory device is further equipped with one or more devices that generate light and transmit the light into the substrate, and one or more devices that cause the phase change material to change between the amorphous and crystalline phases thereof. At least one optical sensing device detects light that passes into the phase change material to the optical sensing device and generates electrical signals based thereon, which are converted into bit values if they exceed a threshold.

Abstract: A nonvolatile storage device adapted for use with computers, workstations and other processing apparatuses. The storage device includes a printed circuit board, a nonvolatile memory array comprising at least two sub-arrays that contain nonvolatile solid-state memory devices, and control circuitry for interfacing with the processing apparatus. The control circuitry includes an abstraction layer and at least two memory control units configured to communicate data, address and control signals with the sub-arrays of the memory devices. A bus connects each memory control unit to a corresponding one of the sub-arrays. The control circuitry further includes a crossbar switch that functionally connects each memory control unit to the abstraction layer. The storage device is capable of overcoming limitations of current SSD designs by enabling independent read and write transfers (accesses) to the memory devices of the storage device, including concurrent read and write accesses.