Patents Assigned to OEPic Semiconductors, Inc.
  • Patent number: 11757255
    Abstract: A method of forming a flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising: forming a VCSEL pillar array; applying a dielectric layer to the VCSEL pillar array, the dielectric layer filling trenches in between pillars forming the VCSEL pillar array and covering the pillars; planarizing the VCSEL pillar array to remove the dielectric layer covering the pillars exposing a metal layer on a top surface of the pillars; applying a metal coating on the metal layer on a top surface of the pillars, the metal layer defining a contact pattern of the VCSEL pillar array; and applying solder on the metal coating to flip chip mount the VCSEL pillar array to a substrate package.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: September 12, 2023
    Assignee: OEpic Semiconductors, Inc.
    Inventor: Yi-Ching Pao
  • Patent number: 11424595
    Abstract: A backside Vertical Cavity Surface Emitting Laser (VCSEL) has a substrate. A first mirror device is formed on the substrate. An active region is formed on the first mirror device. A second mirror device is formed on the active region. A pillar is formed by directional Inductive Coupled Plasma-Reactive Ion Etcher (ICP-RIE). The pillar exposes a portion of the first mirror device, the active region and the second mirror device. A first metal contact is formed over a top section of the pillar. A second metal contact is formed on the substrate. An opening formed in the second metal contact and aligned with the pillar.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 23, 2022
    Assignee: OEPIC Semiconductors, Inc.
    Inventors: Yi-Ching Pao, Majid Riaziat, Ta-Chung Wu, Wilson Kyi, James Pao
  • Patent number: 11424597
    Abstract: A vertical-cavity surface-emitting laser (VCSEL) has a substrate formed of GaAs. A pair of mirrors is provided wherein one of the pair of mirrors is formed on the substrate. A tunnel junction is formed between the pair of mirrors.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: August 23, 2022
    Assignee: OEPIC Semiconductors, Inc.
    Inventors: Ping-Show Wong, Jingzhou Yan, Ta-Chung Wu, James Pao, Majid Riaziat
  • Patent number: 11283240
    Abstract: A backside Vertical Cavity Surface Emitting Laser (VCSEL) has a substrate. A first mirror device is formed on the substrate. An active region is formed on the first mirror device. A second mirror device is formed on the active region. A pillar is formed by directional Inductive Coupled Plasma-Reactive Ion Etcher (ICP-RIE). The pillar exposes a portion of the first mirror device, the active region and the second mirror device. A first metal contact is formed over a top section of the pillar. A second metal contact is formed on the substrate. An opening formed in the second metal contact and aligned with the pillar.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: March 22, 2022
    Assignee: OEPIC SEMICONDUCTORS, INC.
    Inventors: Yi-Ching Pao, Majid Riaziat, Ta-Chung Wu, Wilson Kyi, James Pao
  • Patent number: 11264780
    Abstract: A flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package has a VCSEL pillar array. A first metal contact is formed over a top section of each pillar of the VCSEL pillar array. A second metal contact is formed on a back surface of the VCEL pillar array. An opening is formed in the second metal contact and aligned with the pillars of the VCSEL pillar array. Solder tip is applied on each pillar of the VCSEL pillar array to flip chip mount the VCSEL pillar array.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 1, 2022
    Assignee: OEPIC SEMICONDUCTORS, INC.
    Inventor: Yi-Ching Pao
  • Patent number: 11233377
    Abstract: A method of forming a flip chip backside Vertical Cavity Surface Emitting Laser (VCSEL) package comprising: forming a VCSEL pillar array; applying a dielectric layer to the VCSEL pillar array, the dielectric layer filling trenches in between pillars forming the VCSEL pillar array and covering the pillars; planarizing the VCSEL pillar array to remove the dielectric layer covering the pillars exposing a metal layer on a top surface of the pillars; applying a metal coating on the metal layer on a top surface of the pillars, the metal layer defining a contact pattern of the VCSEL pillar array; and applying solder on the metal coating to flip chip mount the VCSEL pillar array to a substrate package.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: January 25, 2022
    Assignee: OEPIC SEMICONDUCTORS INC.
    Inventor: Yi-Ching Pao
  • Patent number: 11201251
    Abstract: A photodiode has a substrate. A mesa structure is formed on the substrate, wherein the mesa structure has an n region containing an n type dopant formed on the substrate, an intermediate region positioned on the n region and a p region formed on the intermediate region and containing a p type dopant. A contact is formed on a top surface of the mesa and attached to the p region. The contact is formed around an outer perimeter of the mesa. The mesa has a diameter of 30 um or less.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: December 14, 2021
    Assignee: OEPIC SEMICONDUCTORS, INC.
    Inventors: Yi-Ching Pao, Majid Riaziat, Ta-Chung Wu
  • Patent number: 10840106
    Abstract: A method of semiconductor device fabrication that enables fine-line geometry lithographic definition and small form-factor packaging comprises: forming contacts on a metal layer of the semiconductor device; applying a protective mask layer over active regions and surfaces of the contacts having rough surface morphology; planarizing a surface of the semiconductor device until the protective mask layer is removed and the surfaces of the contacts having rough surface morphology are planarized; and forming contact stacks on the surfaces of the contacts which are planarized.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: November 17, 2020
    Assignee: OEPIC SEMICONDUCTORS, INC.
    Inventors: Yi-Ching Pao, James Pao, Majid Riaziat, Ta-Chung Wu
  • Patent number: 10658998
    Abstract: A method for forming an acoustic resonator comprising: forming a piezoelectric material on a first substrate; and applying the piezoelectric material to a second substrate on which the acoustic resonator is fabricated upon.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: May 19, 2020
    Assignee: OEPIC SEMICONDUCTORS, INC.
    Inventors: Majid Riaziat, Yu-Min Houng
  • Patent number: 8546237
    Abstract: A method of transferring an epitaxial film from an original substrate to a destination substrate comprises: growing an epitaxial film grown with a sacrificial layer on the original substrate; patterning the epitaxial film into a plurality of sections; attaching the plurality of sections to a stretchable film; removing the plurality of sections attached to the stretchable film from the original substrate; stretching the sections apart as needed; and attaching a permanent substrate to the plurality of sections; and trimming the sizes of the sections as needed for precise positioning prior to integrated circuit device fabrication.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: October 1, 2013
    Assignee: Oepic Semiconductors, Inc.
    Inventor: Majid Riaziat
  • Patent number: 6920161
    Abstract: Various methods and apparatuses extend the useful operation speed of TO-can optoelectronic packages up to speeds of 10 Gbps and beyond.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: July 19, 2005
    Assignee: OEPic Semiconductors, Inc.
    Inventors: Majid Leondard Riaziat, Ching-Kung Tzuang, Yi-Ching Pao