Patents Assigned to Oki Electric Company
  • Patent number: 6393006
    Abstract: After the switch of a CDMA/AMPS dual-mode portable terminal device is turned ON, the device operates to search for operation history so as to investigate a previously caught channel at step P-3. When a previously caught channel is a CDMA channel, a channel scanning is started from a CDMA system. When a previously caught channel is an AMPS channel, a channel scanning is started from an AMPS system. Usually, when a portable terminal device is restarted, the device is restarted in the same area as in a previous time. Therefore, the device operates to store a previously caught channel and a previously used PN value, while a channel scanning is started from the PN value of said channel. In this way, it is allowed to reduce a time necessary for the above search until a proper channel is caught.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: May 21, 2002
    Assignee: Oki Electric Company Industry Co., Ltd.
    Inventor: Yasunari Kajihara
  • Patent number: 5693139
    Abstract: A cycle of alternately or cyclically introducing external gases containing molecules of component elements of a compound semiconductor to be formed on a substrate is repeated while appropriately controlling the pressure, substrate temperature and gas introduction rate in a crystal growth vessel, so that a monocrystal which is dimensionally as precise as a single monolayer can grow on the substrate by making use of chemical reactions on the heated substrate surface.Doped molecular layer epitaxy of a compound semiconductor comprising individual steps of introducing and evacuating a first source gas, introducing and evacuating a second source gas, and introducing and evacuating an impurity gas which contains an impurity element. The doped impurity concentration varies almost linearly with the pressure during doping in a wide range.
    Type: Grant
    Filed: June 15, 1993
    Date of Patent: December 2, 1997
    Assignees: Research Development Corporation of Japan, Jun-Ichi Nishizawa, Oki Electric Company, Soubei Suzuki
    Inventors: Junichi Nishizawa, Hitoshi Abe, Soubei Suzuki
  • Patent number: 4582565
    Abstract: A method of fabricating integrated semiconductor circuit devices with improved surface planarity. An oxidation-resistant masking layer is deposited over the surface of a semiconductor body and the walls of vertical trenches of a given width formed in the semiconductor body surface. The masking layer is removed in part from predetermined portions of the semiconductor body surface. A polycrystalline semiconductor material is deposited over the semiconductor body surface to bury the trenches, followed by continuous partial removal of the polycrystalline semiconductor material and the semiconductor body at portions corresponding to the predetermined portions of the semiconductor body surface to a predetermined surface level lower than the semiconductor body surface.
    Type: Grant
    Filed: August 8, 1984
    Date of Patent: April 15, 1986
    Assignee: Oki Electric Company Industry, Ltd.
    Inventor: Akira Kawakatsu