Abstract: A communication method in which an operation, such as authentication, required when a new communication terminal participates in a mesh network is carried out in a more efficient manner. A second communication terminal that has already established an adjacent communication link with at least two first communication terminals, out of a plurality of communication terminals, distributes an adjacent terminal list including terminal identifiers of the first communication terminals along with a temporal key generated by the second communication terminal. One of the first communication terminals that received the adjacent terminal list and the temporal key distributes adjacent registration information, which is generated using a second temporal key.

Abstract: A synchronized CDM communication system performs 1-to-N communication by CDM between a central office and first to N-th optical network units (ONU). The synchronized CDM communication system adds structural elements for realizing a connection state acquisition section to a conventional synchronized CDM communication system. A central office includes a presence check section, a ranging processing section and the connection state acquisition section. The presence check section checks the ONUs that are connected with the central office and the ONUs that are not connected. The ranging processing section performs transmission timing adjustments for the ONUs that are connected. The connection state acquisition section verifies whether all of ONUs are connected with the central office, and performs a discovery of a ONU, among the ONUs that were not connected at the time of the check, that has resumed participation in communication since the check ended.

Abstract: A gateway device includes plural electronic circuit boards with redundant structures, between first and second networks, which are different. The gateway device receives data provided through the first network and, after applying data processing, outputs data to the second network. Data processing reference timings and time information, which are common in the gateway device, are shared, the data processing is executed in synchronization with the reference timings, and synchronized packets are provided. System switching between the electronic circuit boards is executed in accordance with the time information. Thus, packet outputs are synchronously switched.

Abstract: A branching filter package has a SAW filter chip housing area which houses a piezo electric base, on which a transmitting SAW filter and a receiving SAW filter having a different frequency passing band with each other, are formed, and an impedance matching circuit and a branching circuit for the transmitting SAW filter and the receiving SAW filter.

Abstract: Speech telephones are incorporated in a LAN, and, for example, when a voice telephone 5 communicates with another voice telephone 8, call control is performed through exchange of information between a PC 1 and a PC 4, juxtaposed with the voice telephones, respectively, via a LAN hub 10, a LAN switching unit 50, and a LAN hub 20. Speech data of the respective telephones 5, and 8 are packetized in the data block of a MAC frame by concentrators 30, and 40 for voice telephones, respectively, and relayed to LAN-SW interfaces 30a, and 40a. Frames having a function of absorbing fluctuation are applied to the data block of the interfaces 30a and 40a. Respective voice data packetized according to the MAC address of the MAC frame are delivered to the voice telephones 5, and 8, respectively, via the LAN switching unit 50, and the concentrators 30, and 40 for voice telephones.

Abstract: A purpose of the present invention is to provide a micro-lens enabling in a simple and highly accurate manner to assess an amount of misalignment with an optical axis generated by an error in a process of manufacturing a micro-lens. According to the present invention, the micro-lens manufactured using a semiconductor lens is provided with a lens portion, a peripheral portion located outside the lens portion and a mark for assessment formed near the peripheral portion during a process of manufacturing the lens portion.

Abstract: A branching filter package has a SAW filter chip housing area which houses a piezo electric base, on which a transmitting SAW filter and a receiving SAW filter having a different frequency passing band with each other, are formed, and an impedance matching circuit and a branching circuit for the transmitting SAW filter and the receiving SAW filter.

Abstract: A moving image encoding device that encodes a difference between a predicted image and an original image is provided. The predicted image is generated using a weighted reference image, for which a weight is multiplied with and an offset is added to a reference image. The moving image encoding device includes an image data reduction section and a weighting estimation section. The image data reduction section reduces data volumes of the original image and the reference image while retaining characteristics of the original image and the reference image. The weighting estimation section estimates weighting parameters on the basis of image data of the original image and reference image of which the data volumes have been reduced by the image data reduction section.

Abstract: A branching filter package has a SAW filter chip housing area which houses a piezo electric base, on which a transmitting SAW filter and a receiving SAW filter having a different frequency passing band with each other, are formed, and an impedance matching circuit and a branching circuit for the transmitting SAW filter and the receiving SAW filter.

Abstract: A branching filter package has a SAW filter chip housing area which houses a piezo electric base, on which a transmitting SAW filter and a receiving SAW filter having a different frequency passing band with each other, are formed, and an impedance matching circuit and a branching circuit for the transmitting SAW filter and the receiving SAW filter.

Abstract: In a clock signal extraction system, an optical modulator modulates an input optical signal having its clock frequency equal to a first or second frequency with a modulation electrical signal having its frequency equal to the average of the first and second frequencies to output a modulated optical pulse signal to a phase comparator, which receives a reference electrical signal generated by a reference signal generator and having its frequency half as high as a difference between the first and second frequencies to compare in phase the modulated optical pulse signal with the reference electrical signal to output a resultant phase comparison signal to a modulation electrical signal generator, which in turn outputs a modulation electrical signal to the optical modulator and clock signal generator, which generates a signal with the modulation and reference electrical signals mixed, and outputs the signal at first or second frequency as a clock signal.

Abstract: An optical communication system has two or more active interfaces, each controlling the transmission and reception of optical signals between a communication network and one or more subscriber terminals according to control information pertaining to the individual subscriber terminals. The control information used by all the active interfaces is stored in a memory. The optical communication system also has a standby interface that is functionally equivalent to the active interfaces, and an optical switching apparatus that switches data transmission paths among the network, the active and standby interfaces, and the subscriber terminals. If a fault is detected in an active interface, the standby interface extracts the control information of the faulty interface from the memory, and the optical switching apparatus switches the data transmission paths so that the standby interface replaces the faulty interface.

Abstract: According to the present invention, a method for fabricating a three-dimensional acceleration sensor, comprising: providing a semiconductor substrate having first and second surfaces; forming an insulating layer on the first surface of the semiconductor substrate; forming an active layer on the insulating layer; forming a plurality of openings on the active layer at a first region, which is to be located above a movable mass with a predetermined space; selectively removing the insulating layer located under the first region in a wet-etching process through the plurality of openings; and selectively removing the active layer to form a groove separating the first region from a movable mass.

Abstract: An optical multiplexing apparatus converts input signals from multiple channels to an optical signal including optical pulses multiplexed on the time axis, transmits the optical signal, and controls the average power of the transmitted optical signal so as to maintain constant transmission quality even if the input signal on one or more channels is lost. For example, the average power may be held at a target value that varies according to the combined duty cycle of the multiplexed optical pulses. Alternatively, the average optical power may be held constant and dummy signals may be inserted to replace lost input signals, or to fill idle channels until signal input begins.

Abstract: A semiconductor device including a semiconductor chip having an electric circuit on a surface thereof, and an electrode pad formed on the surface of the semiconductor chip and which is electrically connected to the electric circuit. A conductive pattern is electrically connected to the pad, and a sealing resin covers the electric circuit and the conductive pattern. A part of the conductive pattern is exposed from the sealing resin, and a plurality of grooves are formed on the part of the conductive pattern. The plurality of grooves are disposed apart from each other and along a direction of stress of the expanding semiconductor chip. An external electrode is electrically connected to the conductive pattern. Stress of the external electrodes is thus relieved and as a result, reliability of the semiconductor device can be improved, because deterioration of the connecting quality can be prevented.

Abstract: An interrupt signal processing apparatus, when receiving an interrupt requesting signal from one device, writes a pulse signal generated by an interrupt setting pulse generating section to a register. The interrupt signal processing apparatus, when receiving an interrupt clearing request signal from the other device, clears the register by using a pulse signal fed from the interrupt clearing pulse generating section and outputs the interrupt permission signal to the one device. When a clock speed of the other device is lower than that of the one device and when pulse generation is controlled by a control signal fed from the clearing pulse generating section of the other device, while the pulse signal fed from the other device is input to the delay circuit, a time delay is provided to operations of the second synchronization section. Thus, smooth interruption can be implemented regardless of the clock speed.

Abstract: A code division multiple access receiver estimates symbol values transmitted by different stations by despreading a combined received signal, weights the estimated symbol values by use of weighting factors calculated for the different stations, respreads the weighted symbol values to estimate the interference due to each station, and subtracts the estimated interference from the received signal to produce a residual signal. The weighting factors can be calculated from the residual signal; the weighting factors are calculated so as to minimize the power of the residual signal. The weighting factors are adjusted at certain intervals, preferably at intervals determined from the rate of fading of the received signal.

Abstract: A protective film (14) on a conductor (11d), where a contact hole (22) is to be formed, is removed in advance in a forming process of an etched-away opening (20) to expose the top portion of the corresponding conductor (11d) from the top surface of an insulating film (15), which has buried therein the conductor (11d) covered with the protective film. The etched-away opening (20) is refilled with the same kind of material as that for the insulating film (15), and then two contact holes, one (21) that opens to the semiconductor substrate (10) substantially devoid of the protective film and the other (22) that opens to the conductor (11d), are formed by simultaneous etching under substantially the same condition.

Abstract: A gate oxide layer 11 and a poly-silicon layer 12 are formed on a silicon substrate 10. A tungsten silicide (WSi) layer that includes dopant is formed by a sputtering method or CVD as the metal silicide layer. This layer is designated a first wiring pattern layer 13. Subsequently, a gate G is formed by removing the surrounding portion of the gate oxide layer 11, the poly-silicon layer 12 and the first wiring pattern layer 13, and an insulator film 14 is formed by thermal oxidation. Then, a first insulator layer 15 is formed from BPSG, and a contact hole 16 is formed through the first insulator layer 15. After that, a second wiring pattern layer 17 is formed by CVD for covering the first insulator layer 15 as well as the contact hole 16, BPSG is deposited on the second wiring pattern layer 17, and becomes a second insulator layer 18 through thermal treatment. The concentration of the dopant in the first wiring pattern layer 13 equals or is larger than that in the second wiring pattern layer 17.

Abstract: A semiconductor memory device includes word lines, bit lines, and memory cells. Each of the memory cells is coupled to a corresponding one of the word lines and a corresponding one of the bit lines. The semiconductor memory device also includes a first node supplied with a first voltage level, a second node supplied with a second voltage level, a third node, and decoders. Each of the decoders is coupled among the second node, the third node, and a corresponding one of the word lines and also selectively couples either one of the second node and the third node to the corresponding word line in response to an address signal. The semiconductor memory device further includes a first voltage signal supply circuit, coupled to the first node and the third node, which couples the first node to the third node according to a control signal, and a second voltage signal supply circuit, coupled to the second node and the word lines, which couples the second node to the word lines according to the control signal.