Patents Assigned to Oki Semiconductor
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Patent number: 8048768Abstract: A method of fabricating a joined wafer has an exposure process which comprises a device formed-area exposure process of exposing by a stepper such that parts of the photosensitive adhesive layer formed over a surface of the transparent wafer or the device formed wafer are removed, the parts corresponding to the device formed areas when the transparent wafer and the device formed wafer are stuck together; and a wafer periphery exposure process of exposing such that a portion of the photosensitive adhesive layer over the periphery of the transparent wafer is left.Type: GrantFiled: July 1, 2009Date of Patent: November 1, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Shigeru Yamada
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Patent number: 8049291Abstract: A sensor includes a substrate provided with a circuit element forming region and a photodiode forming region, the substrate having a silicon substrate, an insulating layer on the silicon substrate, and a silicon layer on the insulating layer; a photodiode in the silicon layer; a circuit element in the silicon layer; a first interlayer insulating film formed over the silicon layer; a first light-shielding film on the first interlayer film and having an opening in the photodiode forming region; and a first inter-region light-shielding plug arranged between the two regions, for connecting the silicon substrate and the first light-shielding film.Type: GrantFiled: March 14, 2008Date of Patent: November 1, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Masao Okihara
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Publication number: 20110261627Abstract: In a semiconductor nonvolatile memory device, nonvolatile memory cells are plurally arranged in a memory array portion. An output circuit outputs setting information selected from plural sets of setting information to generate reference currents with different current values. A reference current circuit generates a reference current with a current value according to the setting information outputted from the output circuit. An amplifier circuit compares a cell current outputted from a selected memory cell of the memory array portion with the reference current generated by the reference current circuit.Type: ApplicationFiled: April 25, 2011Publication date: October 27, 2011Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Hiroyuki TANIKAWA
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Publication number: 20110260770Abstract: A semiconductor device for monitoring batteries or cells connected in series has a selector switch that selects one of the batteries or cells and outputs voltages obtained from its positive and negative terminals. A pair of buffer amplifiers receives these voltages at high-impedance input terminals and output corresponding voltages to a level shifter. The level shifter generates an output voltage equal to the difference between the outputs of the buffer amplifiers. By preventing current flow between the selector switch and the level shifter, the buffer amplifiers reduce the output droop that occurs at the beginning of a voltage measurement, even if the semiconductor device is connected to the batteries or cells through a low-pass filter circuit with a comparatively large time constant. Measurement time is shortened accordingly.Type: ApplicationFiled: April 25, 2011Publication date: October 27, 2011Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Masaru SEKIGUCHI
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Patent number: 8044950Abstract: A driver circuit usable for a display panel can generate an output signal in response to an input pulse signal supplied to only one input signal terminal thereof. The driver circuit includes a pulse generating circuit for generating an output signal at the output terminal. The pulse generating circuit has a first and second differential input stage for respectively driving a push-pull construction of output transistors in response to the input pulse signal supplied through the input signal terminal with respect to the push-pull output, whereby to simplify the circuitry, operate at a high slew rate, and decrease electric current consumption.Type: GrantFiled: December 19, 2006Date of Patent: October 25, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Masanori Satou
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Patent number: 8045349Abstract: A charge pump-type DC/DC converter is provided that steadily operates even when boosting reference voltage is low. A PMOS transistor for short-circuiting an output terminal of a charge pump of an initial stage with a booster reference voltage is provided to eliminate the influence of a parasitic diode of a PMOS transistor within the charge pump of the initial stage during build-up. The PMOS transistor is controlled by the voltage of another charge pump and the short-circuit described above is released by the increase of the output voltage of the other charge pump.Type: GrantFiled: October 19, 2007Date of Patent: October 25, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Munenori Nakamura
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Patent number: 8044507Abstract: A sealing apparatus for sealing by resin a semiconductor wafer having semiconductor elements on its surface. The apparatus includes an upper mold and a tower mold having an area where the semiconductor wafer is mounted, the lower mold having an uneven surface in the area and a shock absorber under the lower mold.Type: GrantFiled: September 14, 2010Date of Patent: October 25, 2011Assignee: OKI Semiconductor Co., Ltd.Inventor: Jiro Matsumoto
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Patent number: 8045630Abstract: A detector of patterns corresponding to pilot symbols is capable of detecting patterns of SP symbols promptly without using a TMCC signal. The SP location detector includes a multiplier which multiplies received signals generated by demodulating OFDM modulation signals in which pilot symbols are dispersively disposed in accordance with four types of patterns and which are transmitted periodically by a pseudo-random number bit sequence, four arithmetic circuits which are respectively provided corresponding to the four types of patterns and which respectively extract pilot symbols corresponding to respective patterns from results of multiplication by the multiplier and calculate sums of phase differences between the extracted pilot symbols, followed by outputting absolute values thereof, and a pattern detection circuit which detects the corresponding arithmetic circuit maximum in the calculated absolute value from within the four arithmetic circuits.Type: GrantFiled: September 27, 2007Date of Patent: October 25, 2011Assignee: Oki Semiconductor Co., Ltd.Inventors: Masato Tanaka, Hiroji Akahori
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Patent number: 8042392Abstract: An acceleration sensor has a semiconductor acceleration sensor chip and a case. The semiconductor acceleration sensor chip has a fixed portion, a plummet portion surrounding the fixed portion without contacting the fixed portion, and a beam portion connecting the fixed portion and the plummet portion, the thickness of the beam portion being thinner than the thickness of the fixed portion. The case has a cavity housing the semiconductor acceleration sensor chip, and a projection portion formed on the bottom face of the cavity, the bottom face of the fixed portion being fixed to the top face of the projection portion.Type: GrantFiled: December 29, 2009Date of Patent: October 25, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Yoshihiko Ino
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Patent number: 8044731Abstract: There is provided an oscillator circuit including: a current source; a resonant unit; an oscillation amplification unit connected to the current source and connected in parallel to the resonant unit; a feedback resistor connected in parallel to the oscillation amplification unit; a switch unit having a first end connected to the current source side of the oscillation amplification unit; a replica circuit connected between a second end of the switch unit and a ground side of the oscillation amplification unit and having a configuration identical to a configuration of the oscillation amplification unit; and a level detecting unit that detects an input voltage of the oscillation amplification unit, and, when the detected input voltage is higher than a bias voltage level at a time of oscillation, cause the switch unit to allow a current from the current sources to bypass through the replica circuit.Type: GrantFiled: January 27, 2010Date of Patent: October 25, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Kenji Arai
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Patent number: 8044484Abstract: The present invention provides an ultraviolet detecting device which comprises a silicon semiconductor layer having a thickness ranging from greater than or equal to 3 nm to less than or equal to 36 nm, which is formed over an insulating layer, lateral PN-junction type first and second photodiodes formed in the silicon semiconductor layer, an interlayer insulating film formed over the silicon semiconductor layer, a first filter layer made of silicon nitride, which is formed over the interlayer insulating film provided over the first photodiode and causes light lying in a wavelength range of an UV-B wave or higher to pass therethrough, and a second filter layer made of silicon nitride, which is formed over the interlayer insulating film provided over the second photodiode and allows light lying in a wavelength range of an UV-A wave or higher to pass therethrough.Type: GrantFiled: October 29, 2010Date of Patent: October 25, 2011Assignee: Oki Semiconductor Co., Ltd.Inventors: Noriyuki Miura, Tadashi Chiba
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Patent number: 8044518Abstract: A second semiconductor chip and a junction member are mounted on a first semiconductor chip formed with a plurality of first pads on a surface thereof. A resin encapsulating body is provided which seals the first semiconductor chip, the second semiconductor chip and the junction member. The second semiconductor chip includes a plurality of second pads arranged in a central part thereof. The junction member includes first junction pads, second junction pads and connecting portions which connect the first junction pads and the second junction pads respectively. Electrical connections of the second semiconductor chip from the second pads include connections to connecting terminals and connections to the connecting terminals or the first semiconductor chip from the second junction pads via the first junction pads.Type: GrantFiled: October 8, 2004Date of Patent: October 25, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Yasufumi Uchida
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Publication number: 20110255642Abstract: Suitable gain control is achieved at low cost. In a receiving apparatus, an RF signal that is amplified by an RF amp is converted to an IF frequency by a frequency conversion unit and amplified by an IF amp, then the output signal from the IF amp that was converted to a digital signal by an ADC is inputted to a digital processing unit. The output from the ADC is then filtered to a desired frequency by a digital filter and inputted to the digital processing unit. In the digital processing unit the signal power before filtering by the digital filter and the signal power after filtering by the digital filter are measured, and the power difference is calculated. Based on the power difference, which indicates the ratio of unnecessary power, the digital processing unit controls the gain ratio of the RF amp and IF amp.Type: ApplicationFiled: April 15, 2011Publication date: October 20, 2011Applicants: OKI SEMICONDUCTOR CO., LTD., CASIO COMPUTER CO., LTD.Inventors: Hiromune Nagai, Shinpei Matsuda, Hiroji Akahori
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Publication number: 20110254616Abstract: A boosting circuit of charge pump type includes: charging portion for applying an input voltage to a first capacitor; double boosting portion for applying the input voltage to a second capacitor and applying a sum of the input voltage and a voltage across the first capacitor to an output capacitor in a first predetermined period after start of a boosting operation; and triple boosting portion for repeating in order, after end of the first predetermined period, a step of applying the sum of the input voltage and the voltage across the first capacitor to the second capacitor and a step of applying a sum of the voltage across the first capacitor and a voltage across the second capacitor to the output capacitor.Type: ApplicationFiled: March 18, 2011Publication date: October 20, 2011Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Hiroaki Kawano
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Patent number: 8039323Abstract: A semiconductor device includes a semiconductor layer with an impurity of a first conductivity type diffused therein, and a local insulating layer, source layer, and a drain layer formed therein. The drain layer has an impurity of a second conductivity type opposite to the first conductivity type. A gate electrode is formed over the semiconductor layer extending from over the local insulating layer to the source layer. A low-concentration diffusion layer is formed in the semiconductor layer below the drain layer. First and second gate insulating films are formed between the gate electrode and the semiconductor layer, and respectively extending from an end, on the source layer side, of the gate electrode to the local insulating layer without reaching the local insulating layer, and extending from an end on another side of the local insulating layer to the source layer.Type: GrantFiled: May 4, 2010Date of Patent: October 18, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Hiroyuki Tanaka
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Patent number: 8039922Abstract: When a positive voltage of V1 is applied to a drive capacitor with a braking voltage V2 at 0V, a moveable electrode moves toward the drive electrode, and a capacitance C of a tunable capacitor becomes smaller. When the braking voltage V2 is applied a lower portion brake electrode of the brake capacitor moves in a horizontal direction, such that the inter electrode separation distance between an upper portion brake electrode and the lower portion brake electrode becomes 0 ?m. The moveable electrode configured integrally formed with the lower portion brake electrode also moves in the horizontal direction, and the inter electrode separation distance between the moveable electrode and a fixed electrode becomes 0 ?m. Since the two electrodes make contact with each other with a dielectric layer interposed therebetween, the position of the moveable electrode can be stably maintained by frictional force between the electrodes.Type: GrantFiled: July 24, 2009Date of Patent: October 18, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Wei Ni
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Patent number: 8041322Abstract: A radio-frequency receiver includes an RF amplification circuit which amplifies a received RF signal and generates an amplified RF signal, a mixing circuit which converts the amplified RF signal into an intermediate-frequency signal, an IF amplification circuit which generates an amplified IF signal, a first level detection circuit which detects a level of the amplified RF signal, a second level detection circuit which detects a level of the IF signal, a third level detection circuit which detects a level of the amplified IF signal, a RF reference level generation circuit which generates an RF reference level based on one of respective detection signal levels of the first and second level detection circuits, and an RF gain control circuits which controls an amplification gain of the RF amplification circuit so that a detection signal level of the third level detection circuit becomes equal to the RF reference level.Type: GrantFiled: January 26, 2009Date of Patent: October 18, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Hiroji Akahori
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Patent number: 8040213Abstract: In order to provide a thin-film resistor and a manufacturing method thereof capable of restraining reduction of a Q-value of varactor by reducing a parasitic capacitance between the resistor and the substrate, the thin-film resistor includes a semiconductor substrate 10 including an integrated circuit 12 having a plurality of electrode pads 14 placed in a distance from each other in the most upper part of a plurality of stacked interconnections, and the integrated circuit 12 having a passivation film 16 formed between the plurality of electrode pads 14; a secondary interconnections 18 electrically connected to the electrode pads 14; an insulating film 20 formed in a place in between the secondary interconnections 18 on the passivation film 16; and a resistor 26 formed 18 in a predetermined place in between the secondary interconnections 18 on the insulating film 20.Type: GrantFiled: March 26, 2009Date of Patent: October 18, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Kinya Ashikaga
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Patent number: 8039917Abstract: A photodiode includes a first silicon semiconductor layer formed over an insulating layer, a second silicon semiconductor layer formed over the insulating layer, having a thickness ranging from greater than or equal to 3 nm to less than or equal to 36 nm, a low-concentration diffusion layer which is formed in the second silicon semiconductor layer and in which an impurity of either one of a P type and an N type is diffused in a low concentration, a P-type high-concentration diffusion layer which is formed in the first silicon semiconductor layer and in which the P-type impurity is diffused in a high concentration, and an N-type high-concentration diffusion layer which is opposite to the P-type high-concentration diffusion layer with the low-concentration diffusion layer interposed therebetween and in which the N-type impurity is diffused in a high concentration.Type: GrantFiled: February 26, 2008Date of Patent: October 18, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Noriyuki Miura
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Patent number: 8039310Abstract: A semiconductor method comprises a method for making a device comprising: a base; a semiconductor chip provided on the base which includes a first main surface 20a on which a plurality of electrode pads is provided, a surface protecting film provided on the first main surface, a second main surface which opposes the first main surface, and a plurality of side surfaces between the surface of the surface protecting film and the second main surface; an insulating extension portion formed so as to surround the side surfaces of the semiconductor chip; a plurality of wiring patterns electrically connected to the electrode pads, respectively and extended from the electrode pads to the surface of the extension portion; a sealing portion formed on the wiring patterns such that a part of each of the wiring patterns is exposed; and a plurality of external terminals provided on the wiring patterns in a region including the upper side of the extension portion.Type: GrantFiled: August 23, 2006Date of Patent: October 18, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Kiyonori Watanabe