Abstract: An apparatus is operable to receive a digital video signal transmitted over a channel and comprises an operational module configured to operate in a first mode of operation and in a second mode. The apparatus is configured to switch operation of the operational module from the first mode to the second mode in dependence of an estimate of an environment (condition) of the channel.

Abstract: A system for performing LS equalization on a signal in an OFDM system comprises a receiver stage for receiving a modulated signal, a demodulation stage for demodulating the received modulated signal to produce a demodulated signal, a channel estimation stage for processing the demodulated signal to provide an output signal corresponding to a channel frequency response and an equalization stage arranged to process the output signal from the channel estimation stage to produce a channel state information signal. The equalization stage is arranged to use the channel state information signal to operate on the demodulated signal from the demodulation stage to produce an equalized demodulated output signal. There is also disclosed a method for performing LS equalization on a signal in an OFDM system.

Abstract: A processor for performing a Fast Fourier Transform and/or an Inverse Fast Fourier Transform of a complex input signal comprises a first stage for passing the input signal to a second stage when a Fast Fourier Transform procedure is to be performed and for swapping the real and imaginary components of the complex input signal before passing the signal to the second stage if an Inverse Fast Fourier Transform procedure is to be performed. The second stage has first and second radix-4 butterfly elements. A third stage is arranged to switch between first and second operating modes, the second operating mode being for processing a complex conjugate symmetrical input signal. A fourth stage has a plurality of processing units, one or more of the processing units comprising a radix-2 pipelined Fast Fourier Transform processor.

Abstract: An apparatus for demodulating an analogue input signal comprises a hard limiter stage (4) for converting the signal to a two level signal. A digital down converter/low pass filter stage (6) converts the signal to a base band signal, and a symbol synchronization stage (8) extracts symbol timing. An instantaneous phase detector (10) calculates the instantaneous phase of the one or more symbols associated with the input signal. If the input signal has been modulated according to a pi/4DQPSK, pi/2DBPSK, GMSK, or a GFSK modulation scheme, a differential detector (12) determines a difference in the phase between adjacent symbols, a coarse frequency offset compensation stage (14) applies a compensation signal to compensate for frequency offset, and a frequency offset estimation stage (16) updates this compensation signal. A demapper (18) generates a demodulated output signal after compensation by the frequency offset compensation stage.

Abstract: An apparatus for timing recovery in an OFDM system comprises a third order phase lock loop comprising a Fast Fourier Transform stage for receiving a number of input signals in the time domain and transforming the signals to the frequency domain. A phase rotation stage adjusts the phase of one or more of the transformed signals. A frequency offset estimation stage estimates frequency offset between sampled signals and a first accumulator accumulates the frequency offset estimates. A low pass filter couplable to an output of the first accumulator stabilizes the phase lock loop. A second accumulator accumulates outputs of the low pass filter and controls phase rotation in the phase rotation stage. A controller controls timing associated with the window of operation of the Fast Fourier Transform process and is itself controlled by the second accumulator. There is also disclosed a receiver comprising the above apparatus and a method for timing recovery in an OFDM system.

Abstract: An apparatus for demodulating a modulated signal comprises an analog to digital converter (2, 12) for converting an analog modulated input signal to a digital signal. The analog to digital converter is arranged to sample the input signal at a predetermined sampling rate. A digital down converter (4, 14) then receives the digital signal at the sampling rate. The digital down converter has an associated digital intermediate frequency and reduces the frequency of the digital signal to one quarter of the sampling rate. A low pass filter (6, 16) filters selected frequencies from the digital signal. A frequency offset stage (8, 18) applies a modification to the frequency of the filtered signal to reduce frequency offset therein, and a differential demodulator (10, 20) demodulates the signal after modifying the frequency to reduce the frequency offset. There is also disclosed a method for demodulating a signal.

Abstract: An encoder system for encoding a signal according to any number of FEC and/or channel codes comprises a shift register, an array of MOD/XOR stages, and a generator matrix stage for controlling the connections between the shift register and the MOD/XOR stages and altering these connections according to a coding format selected by an encoder selection stage. There is also disclosed a decoder system for decoding a signal encoded according to a number of FEC and/or channel codes comprising a decoding stage, and a generator matrix stage for configuring the decoding stage to a decoding code format to be applied an incoming encoded signal. A decoder selection stage is coupled to the generator matrix stage and selects the decoding code format to be used in the decoding process. The decoder selection stage instructs the generator matrix stage to configure the decoding stage according to the selected decoding code format. There is also disclosed a method for encoding and decoding.

Abstract: A system and method for estimating phase offset between a local oscillator and a transmitted input signal in a communication system comprises a differential detector and a phase compensation stage for compensating for phase errors in an output signal from the differential detector. The output signal from the differential detector is rotated in a decision-based rotation stage coupled to the outputs of the differential detector and the phase compensation stage. The rotation is based on a decision made using the output signal from the phase compensation stage. An accumulation stage accumulates the output signal from the decision-based rotation stage for a number of symbols in the transmitted input signal. A normalization stage normalizes the output signal from the accumulation stage and the normalized output signal corresponds to a phase offset of the local oscillator relative to the transmitted input signal.

Abstract: A method for demapping dual carrier modulated COFDM signals comprises normalizing an estimated channel state information signal to obtain a normalized channel state information signal, determining a Y-domain weighting factor from the normalized channel state information signal, determining an X-domain weighting factor from the normalized channel state information signal, performing equalization on a received data OFDM signal to obtain an equalized data signal, weighting an equalized data signal using the Y-domain weighting factor and the X-domain weighting factor to generate a weighted input signal of a demapper and performing linear demapping of the weighted input signal in the demapper. There is also disclosed an apparatus for demapping dual carrier modulated COFDM signals and a receiver comprising such an apparatus.

Abstract: A processor for performing a Fast Fourier Transform and/or an Inverse Fast Fourier Transform of a complex input signal comprises a first stage for passing the input signal to a second stage when a Fast Fourier Transform procedure is to be performed and for swapping the real and imaginary components of the complex input signal before passing the signal to the second stage if an Inverse Fast Fourier Transform procedure is to be performed. The second stage has first and second radix-4 butterfly elements. A third stage is arranged to switch between first and second operating modes, the second operating mode being for processing a complex conjugate symmetrical input signal. A fourth stage has a plurality of processing units, one or more of the processing units comprising a radix-2 pipelined Fast Fourier Transform processor.

Abstract: A method of calculating internal signals for use in a MAP algorithm is disclosed, comprising the steps of: obtaining first decoding signals by processing received systematic and received encoded symbols of each symbol sequence of a received signal; obtaining unnormalized second decoding signals for the current symbol sequence by processing the first decoding signals of the previous sequence and second decoding signals of the previous sequence; obtaining unnormalized third decoding signals for the current symbol sequence by processing the first decoding signals of the current sequence and third decoding signals of the next sequence; normalizing the unnormalized second and third decoding signals; and wherein at least one of said second decoding signals of the previous sequence and said third decoding signals of the next sequence are unnormalised.

Abstract: A system for performing LS equalization on a signal in an OFDM system comprises a receiver stage for receiving a modulated signal, a demodulation stage for demodulating the received modulated signal to produce a demodulated signal, a channel estimation stage for processing the demodulated signal to provide an output signal corresponding to a channel frequency response and an equalization stage arranged to process the output signal from the channel estimation stage to produce a channel state information signal. The equalization stage is arranged to use the channel state information signal to operate on the demodulated signal from the demodulation stage to produce an equalized demodulated output signal. There is also disclosed a method for performing LS equalization on a signal in an OFDM system.

Abstract: A communications system employs a HARQ method and, for at least some transmission formats, incremental redundancy (IR) signals. For such formats, the multiple IR signals are derived from a single turbo encoded signal by forming multiple permutations of the encoded signal. The permutations are then converted to the coding rate of the selected transmission format. It is demonstrated by simulation that the present proposal achieves a better performance than the known HARQ techniques, while its implementation is simpler. For certain transmission formats, the transmitted signal in response to a retransmission request is identical to the first transmitted signal.

Abstract: A method of estimating the reliability of decoded message bits in a digital communications system is proposed. Message and tail bits are coded and transmitted across a communications channel. The coded message and tail bits are then decoded and it is determined that the decoded message bits have no error when the decoded tail bits have at least one error.

Abstract: A technique is proposed for normalizing the multi-bit output of a RAKE receiver by automatically selecting from it fewer bits which are representative of the data in the CDMA signal. The invention is applicable to a CDMA signal in which the data is transmitted discontinuously and a pilot symbol is inserted into the data sequence and transmitted at a different power level. The proposed technique may be operated either on the basis that the power ratio of the pilot part of the CDMA signal to the data part is known, or alternatively without any knowledge of this power ratio. In both cases the pilot part is used to determine the bit position on which the normalization works, and also the fine adjustment of the data part of the CDMA signal.

Abstract: There is provided an apparatus and method for isolating an in-phase component I and a quadrature component Q of a received IF signal and for filtering the received signal. The apparatus comprises a DDC for sampling the received signal at four times the frequency of the received signal, each sample having an order k and a filter for reducing noise outside a required bandwidth. The filter has n taps and comprises a first filter portion for receiving the samples where k is even and for outputting an in-phase component I of the received signal and a second filter portion for receiving the samples where k is odd and for outputting a quadrature component Q of the received signal. The first filter portion has x taps and the second filter portion has y taps and x+y=n.

Abstract: An automatic gain control system comprises a number of variable gain stages connected in series and a number of sensors, the input of each sensor being connected to a respective output of the variable gain stages. The input of an analogue-to-digital converter is connected to the output of one of the variable gain stages. The input of a control unit is connected to the outputs of the sensors and to the output of the analogue-to-digital converter. The input of a digital-to-analogue converter is connected to the output of the control unit, and the control inputs of each of the variable gain stages is connected to an output of the digital-to-analogue converter. The outputs of the digital-to-analogue converter are used to control the gains of the variable gain stages. Also disclosed is a method for automatically controlling gain in a receiver system.

Abstract: The present invention relates generally to error-correction coding and, more particularly, to a decoder for concatenated codes, e.g., turbo codes. The present invention provides a decoder for decoding encoded data, the decoder comprising: a processor having an input which receives probability estimates for a block of symbols, and which is arranged to calculates probability estimates for said symbols in a next iterative state; normalising means which normalises said next states estimates; a switch that receives both said normalised and said unnormalised next state estimates, the output of the switch being coupled to the input of the processor; wherein the switch is arranged to switch between the normalised and unnormalised next state estimates depending on the iterative state.

Abstract: Multipath interference in a received wireless signal is cancelled by generating an estimated duplicate of the interference and subtracting it from the received signal. The interference duplication is performed in a truncated manner, based on a determination of which multipath signals are present, so as to reduce the complexity and processing requirement of the interference duplication. In particular, the present invention proposed that the truncation is based on a determination of which multipath signals are present, and the properties of those signals. In a first case, the truncation is that only interference between selected pairs of paths are cancelled in MPIC. In a second case, for given pairs of paths cancellation is only performed for a subset of the chips in which the corresponding two paths can cause interference.

Abstract: A receiver for a HARQ communication system includes a buffer for storing a signal derived from a message. The signal is transmitted to the receiver at a first coding rate. The receiver also includes a decoder which accepts signals having a second coding rate, and a rate dematcher which converts signals from the first coding rate to the second coding rate. The rate dematcher is arranged to process either a combination of the received signals (in the case that the received signals are noisy versions of identical signals transmitted within the communications network) or simply the set of received signals. In either case, the dematcher forwards the results to the decoder. Provided that the second coding rate is lower than the first coding rate, the amount of memory required by the buffer is reduced by locating the buffer before the rate dematching unit.