Abstract: A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

Abstract: A time-interleaved circuit includes an input buffer, a plurality of track-and-hold circuits, and a plurality of isolation inductors. The input buffer is configured to receive an input signal having an input voltage and to output an output signal having an output voltage. The track-and-hold circuits are electrically coupled in parallel with each other. Each track-and-hold circuit is electrically coupled in series with the input buffer. Each isolation inductor is electrically coupled to the output of the input buffer and at least one of the track-and-hold circuits.

Abstract: A piecewise linear gain amplifier circuit includes a differential preamplifier and a plurality of transconductors. The differential preamplifier is electrically coupled to a differential input having an input voltage. The transconductors are electrically coupled in parallel with each other. Each transconductor includes a respective differential input that is electrically coupled to a differential output of the differential preamplifier. In addition, each transconductor includes a respective differential output that is electrically coupled to a common differential PWL output. Each transconductor has a different linear input range. An optional attenuation circuit can be electrically coupled in parallel to the differential preamplifier. The differential output of the attenuation circuit can be electrically coupled to a differential input of another transconductor, and that transconductor can have a differential output that is electrically coupled to the common differential PWL output.

Abstract: An analog-to-digital conversion (ADC) system is operated with a duty cycle. During the ON period, the ADC circuits perform analog-to-digital conversions of an analog input signal. During the Standby period, the ADC system is in either a standby state or a foreground calibration state. The ADC system operates in a reduced-power mode in the standby state. In the foreground calibration state, the ADC system performs a portion of a foreground calibration cycle during a calibration time slot. The foreground calibration cycle is performed over multiple calibration time slots. The foreground calibration cycle and the calibration time slots are configurable by changing the values of control registers that represent calibration parameters.

Abstract: A multipath sampling circuit includes an input line electrically having an input voltage, a plurality of voltage amplifiers in parallel electrically with one another, each voltage amplifier having a respective input electrically coupled in series with the input line, each voltage amplifier having a different gain and a different saturation voltage; and a plurality of track-and-hold circuits. The track-and-hold circuits have a first state in which a respective input of each track-and-hold circuit is electrically coupled to an output of a respective amplifier. The track-and-hold circuits have a second state in which the respective input of each track-and-hold circuit is electrically decoupled from the output of the respective amplifier. The track-and-hold circuits can be electrically coupled to a summing circuit, a buffer amplifier, or an operational amplifier.

Abstract: A time-interleaved circuit includes an input buffer, a plurality of track-and-hold circuits, and a plurality of isolation inductors. The input buffer is configured to receive an input signal having an input voltage and to output an output signal having an output voltage. The track-and-hold circuits are electrically coupled in parallel with each other. Each track-and-hold circuit is electrically coupled in series with the input buffer. Each isolation inductor is electrically coupled to the output of the input buffer and at least one of the track-and-hold circuits.

Abstract: A digital-to-analog converter includes an array of capacitors, an array of capacitor switches, positive and negative high-bandwidth reference buffers, positive and negative low-bandwidth reference buffers, and a reference-voltage-selection switch. Each capacitor switch electrically couples a respective capacitor to either a positive or a negative reference voltage line. The reference-voltage-selection switch electrically couples the positive and negative reference voltage lines to either positive and negative high-bandwidth voltages or to positive and negative low-bandwidth voltages. The positive and negative high-bandwidth voltages are produced by the positive and negative high-bandwidth reference buffers. The positive and negative low-bandwidth voltages are produced by the positive and negative low-bandwidth reference buffers.

Abstract: A time-interleaved sampling system includes an input signal having a time-varying analog value and a plurality of samplers. Each sampler is operable in a hold mode and a track mode. In the track mode, the samplers track the analog value of the input signal. In the hold mode, each sampler holds a respective analog value of the input signal that a respective sampler tracked immediately before entering the hold mode. The samplers enter the track mode in a predetermined sequence. After a last sampler in the predetermined sequence enters the track mode, the predetermined sequence is repeated in a loop. At random intervals, a skipped sampler in the predetermined sequence is bypassed from entering the track mode.

Abstract: A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

Abstract: Photo receiver circuits comprising photo diode, a first amplifier, a second amplifier, and a feedback resistor are disclosed. The photo diode receives a light signal producing a photo current and the circuit produces an output voltage proportional to the photo current. In one example, the second amplifier coupled across the photo diode provides a voltage level shift between the input terminal and the output terminal, bootstrapping the parasitic capacitance out.

Abstract: An analog current memory circuit includes a ramp current generator producing a ramp current; a storage transistor, a write-enable transistor, a charge pump transistor, a clock generator producing a clock signal having a first state and a second state, a comparator electrically coupled to the storage transistor and the ramp current generator, a controller electrically coupled to the comparator and the clock generator, and a switch electrically coupled to the controller and the ramp current generator. During the write phase, the controller produces a write-enable signal to turn on the write-enable transistor to produce a stored current in the storage transistor, the stored current being substantially equal to an input current to the analog current memory circuit. During the compensation phase, the switch electrically couples the ramp current generator and the storage transistor to the comparator.

Abstract: A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

Abstract: Integrator circuits comprising switched capacitors, non-switched capacitors, and an op amp. One embodiment is directed to an integrator circuit comprising an op amp having an inverting input, a non-inverting input, an inverting output and a non-inverting output, a first sampling capacitor and a first feedback capacitor, and a first non-switched capacitor. The first feedback capacitor is coupled between the inverting input and the non-inverting output of the op amp, and the first non-switched capacitor is coupled between the negative integrator input and the inverting input of the op amp. During a sampling phase, a positive integrator input is coupled to the first sampling capacitor, and during an integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.

Abstract: Amplifier circuits comprising an input transistor, a load transistor, and a feedback resistor. In one example, one embodiment is directed to an amplifier circuit comprising an input transistor, a load transistor having a control terminal and a reference terminal, and a feedback transistor. The input transistor receives an input signal, the input transistor is electrically coupled to the load transistor and the feedback transistor, the control terminal of the load transistor is electrically coupled to a bias voltage, the feedback transistor is electrically coupled to the load transistor providing negative feedback, and the reference terminal of the load transistor serves as an output of the amplifier circuit.

Abstract: Switched capacitor circuits and charge transfer methods comprising a sampling phase and a transfer phase. Circuits and methods are implemented via a plurality of switches, a set of at least two capacitors, at least one voltage amplifier, and an operational amplifier. In one example, during the sampling phase at least one input voltage is sampled, and during the transfer phase at least a first reference voltage provided by the at least one voltage amplifier is subtracted from the at least one input voltage using the operational amplifier. The same set of at least two capacitors may be used in both the sampling phase and the transfer phase.

Abstract: Amplifier circuits implemented with a buffer amplifier with a voltage gain substantially equal to one. In one example, a continuous-time amplifier is implemented by applying the input source across the input and the output terminals of the buffer amplifier. In another example, a discrete-time amplifier is implemented. During the sampling phase at least one input voltage is sampled, and during the transfer phase at least one capacitor is coupled across the input and the output terminals of a buffer amplifier to effectuate an amplification.