Abstract: The present invention provides a dual conversion gain image sensor comprising: a pixel circuit, through which pixel power supply voltage noise is transferred to a bit line; a power supply noise cancellation circuit with an input to which the pixel power supply voltage is applied, the power supply noise cancellation circuit mimicly producing a first transfer function with the aid of a low conversion gain path, the power supply noise cancellation circuit mimicly producing a second transfer function with the aid of a high conversion gain path; and a comparator. According to the present invention, the low and high conversion gain paths are two independent power supply noise cancellation paths that result in different transfer functions capable of tracking the variation of the pixel power supply voltage in low and high conversion gain modes.

Abstract: An image sensor and an electronic device are disclosed. At least one pixel in the image sensor includes a photodiode, a floating diffusion region and a transfer transistor located between the photodiode and the floating diffusion region. The photodiode includes a carrier-accumulation region, and a gate of the transfer transistor extends up to the carrier-accumulation region. The gate extends away from the floating diffusion region and overlaps over half of a width of the carrier-accumulation region. Since carriers move at a higher speed in a fast transfer channel in the semiconductor substrate around such a gate, increasing the length of the transfer transistor's gate extending away from the floating diffusion region and overlapping range with the carrier-accumulation region can facilitate fast movement of carriers from the carrier-accumulation region through such fast transfer channels to the floating diffusion region, thereby improving overall carrier transfer efficiency and optimizing performance thereof.

Abstract: A back-illuminated sensor chip is disclosed, which includes one or more pixel areas each including a plurality of pixels located in a plane and arranged in a matrix. Each pixel area includes: a central portion consisting of a plurality of first pixels located in vicinity of a center of the pixel area; and a peripheral portion surrounding the central portion and consisting of the other pixels in the pixel area than the first pixels. The plurality of first pixels have a first height in a vertical direction perpendicular to the plane, and the pixels in the peripheral portion have a second height in the vertical direction that is greater than the first height so that the peripheral portion protrudes outward beyond the central portion and is thus located nearer to a light source during imaging than the central portion. As a result, light sensibility of the peripheral portion is increased.

Abstract: Methods and systems for JPEG encoding and decoding are disclosed. In the encoding method, an image is split into 8×8 pixel blocks and the 8×8 pixel blocks are grouped into a number of minimum coded units (MCU's), such that each MCU consists of a constant number of 8×8 pixel blocks. The MCU's are then scanned to forward discrete cosine transform, quantization, zigzag scanning and entropy encoding processes and are subsequently converted into bitstreams according to entropy encoding coding tables. In the entropy encoding process, AC coefficients are run-length encoded, while DC coefficients are not subjected to differential pulse-code modulation. The bitstreams are byte-aligned by stuffing zeroes and compression data for a special JPEG file are generated from the byte-aligned bitstreams. A position table is established, recording positions of the bitstreams in the compression data. The method enables fast positioning of bitstreams corresponding to an image region of interest.

Abstract: A method of manufacturing LCOS panel is disclosed. The method includes: providing a silicon substrate on which at least one conductive pad is formed and a transparent substrate on which a transparent electrode layer is formed; dispensing or coating a sealing material on a predetermined area of the silicon substrate or the transparent substrate; bonding the silicon substrate with the transparent substrate; singulating the bonded silicon substrate and transparent substrate such that at least one space is provided between the silicon substrate and the transparent substrate on an outer side of the sealing material and a part of the transparent electrode layer is exposed in the space; and dispensing a conductive adhesive into the space to connect the transparent electrode layer to the conductive pad. The method is able to achieve a smaller-size of the LCOS panels, a higher production yield and a lower process requirement.

Abstract: A method of fabricating a semiconductor structure is disclosed, in which a pad above a connecting section and metal structures above a functional section are formed from the same metal layer. This design enables the simultaneous formation of the pad and the metal structures by forming a single metal layer and performing thereon a selective etching process, thereby leading to the advantages of process simplification, throughput improvement and cost reduction.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate having a device function layer formed thereon; forming a first opening in the device function layer, the first opening extending through the device function layer and having a side-to-bottom angle of smaller than 90°; and etching the substrate to form therein a second opening by using the device function layer as a mask and the first opening as a mask pattern. A method of fabricating a stacked chip is also disclosed, in which a second opening is formed in the same manner as the fabrication method of the semiconductor device. The fabrication methods are capable of simplifying semiconductor fabrication processes, increasing the throughput of a semiconductor fabrication plant and reducing fabrication cost.

Abstract: A housing for protecting a wafer-level camera module and fixing the wafer-level camera module to a printed circuit board (PCB) includes: four side plates, defining a quadrilateral frame; four supporting plates each fixed to a lower portion of an inner face of a corresponding one of the four side plates, each supporting plate having a top face supporting a portion of the camera module; and four bottom plates each fixed to a lower portion of an outer face of a corresponding one of the four side plates, each bottom plate having a bottom face fixed to the PCB. The housing is capable of addressing the issues of poor housing-PCB soldering, paint falling off and surface scratching and improving the efficiency in UV lamp-utilized UV adhesive curing.

Abstract: The present invention discloses a carrier frequency acquisition method and apparatus in which the structure of a transmission frame includes a short training sequence, the method including: delaying a received short training sequence by L sampling points and multiplying the delayed short training sequence with the original short training sequence to obtain a new sequence; delaying the new sequence by D sampling points and conjugate multiplying the delayed new sequence with the original new sequence; accumulating the results of the conjugate multiplication; and evaluating a phase from the result of the accumulation to estimate carrier frequency offset. With the above method, the present invention is capable of greatly improving the acquisition range of carrier frequency offset while requiring a simple set of hardware.

Abstract: A wafer-level bonding method for fabricating wafer level camera lenses is disclosed. The method includes: providing a lens wafer including lenses arranged in an array and a sensor wafer including sensors arranged in an array; measuring and analyzing an FFL of each lens to obtain a corresponding FFL compensation value for each lens; forming a thin transparent film (TTF) on each sensor of the sensor wafer, and the thickness of TTF is determined by the FFL compensation value of the corresponding lens; aligning and bonding the lens wafer with the sensor wafer having TTFs formed thereon. Since the focal length of each lens is adjusted to compensate the FFL of the lens by adding a TTF of transparent optical material with an index of refraction that is similar to the index of refraction of the sensor cover glass, the FFL variation of each camera lens can be reduced.

Abstract: Methods, system and apparatuses for carrier frequency offset estimation are disclosed. The method includes: receiving a preamble sequence rn with a correlator and correlating the preamble sequence with a locally stored Barker code bn to obtain a correlation result cn; extracting peak values from every L points in cn to form a peak value sequence xn, L being a length of a Barker code that corresponds to the sampling rate; performing frequency offset estimation to xn by using at least two frequency offset estimation apparatuses, the at least two frequency offset estimation apparatuses adopting different delay parameters D; and inputting the results output from the at least two frequency offset estimation apparatuses into a frequency offset combination module to calculate a final carrier frequency offset estimate, whereby accurate frequency estimation can be achieved and an appropriate acquisition range of frequency offset can be ensured.

Abstract: An SD/SDIO host controller is disclosed, which includes a control register and interrupt generation module, an internal DMA module, an SD/SDIO command interface module, an SD/SDIO data interface module, and a frequency divider and trigger/sampling enable signal generation module which is connected to an output end of the control register and interrupt generation module; the frequency divider and trigger/sampling enable signal generation module employs a frequency divider to perform frequency division on a local high-speed clock so as to obtain the operating clock of the SD/SDIO card, and simultaneously generates a trigger/sampling enable signal by the frequency divider and enables the position of the enable signal to be adjustable with respect to the operating clock of the SD/SDIO card. The present invention is capable of solving the setup/hold time issues caused by delay in digital signals.

Abstract: Methods and apparatuses for channel estimation are disclosed. The method includes: converting ?1's in a local Barker code to 0's; receiving a first preamble symbol output from a first Barker correlator and a second preamble symbol output from a second Barker correlator with a symbol determination module, the first preamble symbol being adjacent to the second preamble symbol; multiplying a result output from the symbol determination module with a correlation result output from the cyclic Barker correlator by using a multiplication module so as to obtain a channel estimation response; and receiving channel estimation responses with a time-domain channel data storage unit, and averaging them to obtain a noise-reduced channel estimation response. The channel estimation method and apparatus of the present invention can be achieved based on few hardware resources and low computation complexity.

Abstract: A method for network-based real-time video display is disclosed. The method includes: setting up a connection between an imaging apparatus and a website via a wireless network; producing a video by the imaging apparatus and displaying the video by the website if the imaging apparatus is successfully authenticated, wherein producing a video by the imaging apparatus includes: recording a video and splitting the video into video segments; processing and converting the video segments into a video stream; and uploading the video stream to the website, further wherein, displaying the video by the website includes: offering a display widget to the video stream and creating a display window for the video; embedding the display window in a corresponding display page; and displaying the video through the display window in real time. A system for network-based real-time video display is also disclosed.

Abstract: A signal demodulation method is disclosed, which includes: obtaining a complete transmission code word; calculating estimated values of three non-differential phases of the transmission code based on a majority logic; identifying a most unreliable phase among three non-differential phases and determining the other two reliable phases to obtain their determination values; calculating determination values of the rest two phases based on the two determined phases; and looking up in tables based on determination values of the four phases to obtain incoming bits. The demodulation method of the present invention is capable of sufficiently reducing the effect of noise on signal and effectively improving the signal demodulation performance.

Abstract: A wafer-level bonding method for fabricating wafer level camera lenses is disclosed. The method includes: providing a lens wafer including lenses arranged in an array and a sensor wafer including sensors arranged in an array; measuring and analyzing an FFL of each lens to obtain a corresponding FFL compensation value for each lens; forming a thin transparent film (TTF) on each sensor of the sensor wafer, and the thickness of TTF is determined by the FFL compensation value of the corresponding lens; aligning and bonding the lens wafer with the sensor wafer having TTFs formed thereon. Since the focal length of each lens is adjusted to compensate the FFL of the lens by adding a TTF of transparent optical material with an index of refraction that is similar to the index of refraction of the sensor cover glass, the FFL variation of each camera lens can be reduced.

Abstract: A method of manufacturing LCOS panel is disclosed. The method includes: providing a silicon substrate on which at least one conductive pad is formed and a transparent substrate on which a transparent electrode layer is formed; dispensing or coating a sealing material on a predetermined area of the silicon substrate or the transparent substrate; bonding the silicon substrate with the transparent substrate; singulating the bonded silicon substrate and transparent substrate such that at least one space is provided between the silicon substrate and the transparent substrate on an outer side of the sealing material and a part of the transparent electrode layer is exposed in the space; and dispensing a conductive adhesive into the space to connect the transparent electrode layer to the conductive pad. The method is able to achieve a smaller-size of the LCOS panels, a higher production yield and a lower process requirement.

Abstract: A housing for protecting a wafer-level camera module and fixing the wafer-level camera module to a printed circuit board (PCB) includes: four side plates, defining a quadrilateral frame; four supporting plates each fixed to a lower portion of an inner face of a corresponding one of the four side plates, each supporting plate having a top face supporting a portion of the camera module; and four bottom plates each fixed to a lower portion of an outer face of a corresponding one of the four side plates, each bottom plate having a bottom face fixed to the PCB. The housing is capable of addressing the issues of poor housing-PCB soldering, paint falling off and surface scratching and improving the efficiency in UV lamp-utilized UV adhesive curing.

Abstract: A backside illuminated (BSI) CMOS image sensor is disclosed. The BSI CMOS image sensor includes: a substrate having a front side and a back side, the substrate including a photodiode formed therein, the photodiode being proximate the back side of the substrate; a metal shielding layer covering the back side of the substrate, the metal shielding layer including an opening formed therein, the opening being arranged in correspondence with the photodiode; and a light-absorbing layer formed on each side face of the opening. The light-absorbing layer coated on the side faces of the opening prevents the occurrence of photon cross-talk and hence improves imaging quality of the BSI CMOS image sensor.

Abstract: Method and apparatus for achieving high precision sampling recovery at a relatively low sampling rate. The apparatus includes: a sampling rate conversion module for converting the sampling rate of a received signal to an required sampling rate; a time domain impulse response estimation module for estimating a time domain impulse response of a transmission channel according to data output by the sampling rate conversion module; a high order interpolation module for performing high order interpolation to one or more selected transmission paths after obtaining the time domain impulse response; and a sampling error information extraction module for extracting sampling phase offset information and sampling frequency offset information based on interpolation results and drifts in two consecutive interpolation results of the high order interpolation step. The apparatus is capable of realizing fast high precision locking of sampling phase and correction of sampling frequency offset at a relatively low sampling rate.