Patents Assigned to On-Chip Technolgies, Inc.
  • Publication number: 20080168309
    Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
    Type: Application
    Filed: June 16, 2006
    Publication date: July 10, 2008
    Applicant: On-Chip Technolgies, Inc.
    Inventors: Bulent Dervisoglu, Laurence H. Cooke, Vacit Arat
  • Patent number: 5526025
    Abstract: A method and apparatus for improving bandwidth of sequential access to a display data memory. Display data and tag information related to consecutive data repetitions are stored. No display memory access is needed to output data to the CRT during the time periods when data is being repeated, thus increasing display memory bandwidth. Display data from a location in display memory is stored in a latch, and is output from the latch until the tag information indicates no more data repetitions occur.
    Type: Grant
    Filed: April 19, 1993
    Date of Patent: June 11, 1996
    Assignee: Chips and Technolgies, Inc.
    Inventors: Pierre M. Selwan, David G. Reed, Arun Johary, Morris E. Jones, Jr., Edward P. Hutchins, Mahesh Siddappa