Patents Assigned to On-Chip Technologies, Inc.
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Patent number: 7797595Abstract: Testing of memories that decode a serial stream of address data to access the memory may be performed by either successively halving the number of selected word lines as each address bit is acquired, until a single word line is selected, or by rotating the selection bits in its shift register to select a new set of address lines. As such, a combination of incomplete addressing and rotation can efficiently test large memories by reading and/or writing groups of words. Similar techniques may also be applied to non-memory devices.Type: GrantFiled: June 18, 2008Date of Patent: September 14, 2010Assignee: On-Chip Technologies, Inc.Inventor: Laurence H. Cooke
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Patent number: 7353470Abstract: Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.Type: GrantFiled: July 18, 2005Date of Patent: April 1, 2008Assignee: On-Chip Technologies, Inc.Inventors: Laurence H. Cooke, Bulent I. Dervisoglu
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Publication number: 20070168798Abstract: A new technique to determine the placement of exclusive-ors in each scan string of a chip may be used to achieve improved test vector compression, and this may be used along with methods to minimize the overhead of the exclusive-or logic, to eliminate clock enable logic for multiple scan strings, to minimize the changes to existing test logic insertion and scan string reordering, and to minimize the test vector compression computation time.Type: ApplicationFiled: August 23, 2005Publication date: July 19, 2007Applicant: On-Chip Technologies, Inc.Inventor: Laurence Cooke
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Patent number: 7234092Abstract: A technique to reduce the test data volume and number of scan shift clocks per test pattern by combining the scan inputs with existing values in scan chains and inserting them at additional bit positions along the scan chains in order to reduce the number of shift clocks required to achieve required values at plurality of scan bit positions, and by using multiple taps from the scan chains to form a check-sum in order to reduce the number of scan shift clocks to capture test results.Type: GrantFiled: January 24, 2003Date of Patent: June 19, 2007Assignee: On-Chip Technologies, Inc.Inventor: Laurence H. Cooke
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Patent number: 7200784Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).Type: GrantFiled: September 1, 2004Date of Patent: April 3, 2007Assignee: On-Chip Technologies, Inc.Inventors: Bulent Dervisoglu, Laurence H. Cooke
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Patent number: 7197681Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).Type: GrantFiled: January 5, 2004Date of Patent: March 27, 2007Assignee: On-Chip Technologies, Inc.Inventors: Bulent Dervisoglu, Laurence H. Cooke
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Patent number: 7188286Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).Type: GrantFiled: September 1, 2004Date of Patent: March 6, 2007Assignee: On-Chip Technologies, Inc.Inventors: Bulent Dervisoglu, Laurence H. Cooke
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Publication number: 20070050596Abstract: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.Type: ApplicationFiled: August 23, 2005Publication date: March 1, 2007Applicant: On-Chip Technologies, Inc.Inventor: Laurence Cooke
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Publication number: 20060195746Abstract: Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.Type: ApplicationFiled: July 18, 2005Publication date: August 31, 2006Applicant: On-Chip Technologies, Inc.Inventors: Laurence Cooke, Bulent Dervisoglu
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Patent number: 7080301Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.Type: GrantFiled: October 31, 2005Date of Patent: July 18, 2006Assignee: On-Chip Technologies, Inc.Inventors: Bulent Dervisoglu, Laurence H. Cooke, Vacit Arat
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Publication number: 20060064615Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.Type: ApplicationFiled: October 31, 2005Publication date: March 23, 2006Applicant: On-Chip Technologies, Inc.Inventors: Bulent Dervisoglu, Laurence Cooke, Vacit Arat
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Publication number: 20060041798Abstract: Specific test logic may be added into a semiconductor logic or memory device, which does not change the normal operation of the device, but which allows under test mode the device to perform both parallel read-compare and parallel write operations of the blocks within the device, which provides significant reduction of the overall time to test the device.Type: ApplicationFiled: August 23, 2004Publication date: February 23, 2006Applicant: On-Chip Technologies, Inc.Inventor: Laurence Cooke
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Patent number: 6964001Abstract: An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.Type: GrantFiled: January 30, 2004Date of Patent: November 8, 2005Assignee: On-Chip Technologies, Inc.Inventors: Bulent Dervisoglu, Laurence H. Cooke, Vacit Arat
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Publication number: 20050154948Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).Type: ApplicationFiled: September 1, 2004Publication date: July 14, 2005Applicant: On-Chip Technologies, Inc.Inventors: Bulent Dervisoglu, Laurence Cooke
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Publication number: 20050028060Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).Type: ApplicationFiled: September 1, 2004Publication date: February 3, 2005Applicant: On-Chip Technologies, Inc.Inventors: Bulent Dervisoglu, Laurence Cooke
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Publication number: 20040187054Abstract: An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.Type: ApplicationFiled: January 30, 2004Publication date: September 23, 2004Applicant: On-Chip Technologies, Inc.Inventors: Bulent Dervisoglu, Laurence H. Cooke, Vacit Arat
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Publication number: 20040148554Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).Type: ApplicationFiled: January 5, 2004Publication date: July 29, 2004Applicant: On-Chip Technologies, Inc.Inventors: Bulent Dervisoglu, Laurence H. Cooke
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Patent number: 6687865Abstract: An integrated circuit is described which include a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface, or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.Type: GrantFiled: March 24, 1999Date of Patent: February 3, 2004Assignee: On-Chip Technologies, Inc.Inventors: Bulent Dervisoglu, Laurence H. Cooke, Vacit Arat
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Publication number: 20030229834Abstract: A technique to reduce the test data volume and number of scan shift clocks per test pattern by combining the scan inputs with existing values in scan chains and inserting them at additional bit positions along the scan chains in order to reduce the number of shift clocks required to achieve required values at plurality of scan bit positions, and by using multiple taps from the scan chains to form a check-sum in order to reduce the number of scan shift clocks to capture test results.Type: ApplicationFiled: January 24, 2003Publication date: December 11, 2003Applicant: On-Chip Technologies, Inc.Inventor: Laurence H. Cooke