Patents Assigned to ON Semiconductor
  • Patent number: 11323648
    Abstract: The present invention relates to a solid-state image sensor including a pixel array section including a plurality of unit pixels each having a photoelectric conversion unit, the plurality of unit pixels being arranged in a matrix, a sample-and-hold unit configured to sample and hold a pixel signal output from the unit pixel through a vertical signal line provided in association with column arrangement of the pixel array section, and an analog-to-digital conversion unit configured to convert a pixel signal output from the sample-and-hold unit into a digital signal. Then, the sample-and-hold unit has two sample-and-hold circuits in parallel for one vertical signal line, and at least one of the two sample-and-hold circuits has at least two sampling capacitors.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: May 3, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Kouji Matsuura
  • Patent number: 11322188
    Abstract: A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Lien Linus Lu, Fong-Yuan Chang, Yi-Chun Shih
  • Patent number: 11322719
    Abstract: An organic light emitting diode (OLED) device and the method of fabricating thereof. The OLED device includes a substrate, a display region, a non-display region, and an encapsulation structure covering the display region and the non-display region. The non-display region is composed of a flexible substrate that is bendable, the flexible substrate is curved toward a second surface of the substrate. The non-display region is provided with at least one groove structure at an edge adjacent to the display region, the groove structure extends along a first direction which is parallel to a boundary line between the display region and the non-display region.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: May 3, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xingyong Zhang
  • Patent number: 11322689
    Abstract: A light-emitting element containing a fluorescent material and having high emission efficiency is provided. The light-emitting element contains the fluorescent material and a host material. The host material contains a first organic compound and a second organic compound. The first organic compound and the second organic compound can form an exciplex. The proportion of a delayed fluorescence component in light emitted from the exciplex is higher than or equal to 5%, and the delayed fluorescence component contains a delayed fluorescence component whose fluorescence lifetime is 10 ns or longer and 50 ?s or shorter.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 3, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takahiro Ishisone, Shunsuke Hosoumi, Tatsuyoshi Takahashi, Satoshi Seo
  • Patent number: 11323101
    Abstract: A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal or an output clock signal. The memory state latch circuit is configured to generate the output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and configured to adjust the output clock signal responsive to the latch output signal. The clock trigger circuit is coupled to the latch circuit or the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: May 3, 2022
    Assignee: AIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-I Yang, Fu-An Wu, Yangsyu Lin, Chiting Cheng, Cheng Hung Lee, Chen-Lin Yang
  • Patent number: 11322221
    Abstract: A memory device includes: a memory cell capable of holding data; and an ECC circuit capable of generating a correction code and detecting an error based on the correction code. The memory cell is accessed by a pipeline operation. The pipeline operation includes at least four pipeline stages including a read cycle reading data from the memory cell, an ECC cycle executing generation of the correction code or error detection for the memory cell in the ECC circuit, a wait cycle during which processing for data related to the memory cell is not executed, and a write cycle writing data into the memory cell.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 3, 2022
    Assignees: Sharp Semiconductor Innovation Corporation, TOHOKU UNIVERSITY
    Inventors: Shigeo Ohyama, Tetsuo Endoh
  • Patent number: 11322393
    Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Nien Su, Shu-Huei Suen, Jyu-Horng Shieh, Ru-Gun Liu
  • Patent number: 11318579
    Abstract: An apparatus includes a slurry dispensing arm, multiple nozzles formed on the slurry dispensing arm, and a slurry supply module connected to the slurry dispensing arm. The slurry supply module is configured to provide slurry to the multiple nozzles and the multiple nozzles are configured to dispense the slurry.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Hsieh, Tseng-Hsuan Huang, Chen-Hsiang Liao
  • Patent number: 11322391
    Abstract: Embodiments and methods of an interconnect structure are provided. The interconnect structure includes a via, a trench that has an overlapping area with a top of the via, and a first layer of conducting material that has an overlapping area with a bottom of the via. The interconnect also includes a second layer of conducting material formed in the via, and a third layer of conducting material formed in the trench. The second layer of conducting material is in contact with the first layer of conducting material without a barrier in between the two conducting materials. The absence of the barrier at the bottom of the via can reduce the contact resistance of the interconnect structure.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tz-Jun Kuo, Chien-Hsin Ho, Ming-Han Lee
  • Patent number: 11322562
    Abstract: The present disclosure provides a method of fabricating an organic light-emitting diode (OLED) display panel and an organic light-emitting diode (OLED) display panel. The OLED display panel includes a substrate; a driving circuit layer formed on the substrate; a pixel defining layer; and a light emitting functional layer, which are stacked. Protrusions are provided on a surface of the pixel defining layer away from the driving circuit layer in at least one of a plurality of pixel defining regions, and the light emitting functional layer is formed on the pixel defining layer and covers the sub-pixel regions. By forming the protrusions, a lateral transmission path of charges between adjacent sub-pixels is increased, resulting in a reduction in light leakage.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 3, 2022
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Yang Liu, Yingchun Fan
  • Patent number: 11317806
    Abstract: A wireless sensor device capable of constant operation without replacement of batteries. The wireless sensor device is equipped with a rechargeable battery and the battery is recharged wirelessly. Radio waves received at an antenna circuit are converted into electrical energy and stored in the battery. A sensor circuit operates with the electrical energy stored in the battery, and acquires information. Then, a signal containing the information acquired is converted into radio waves at the antenna circuit, whereby the information can be read out wirelessly.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: May 3, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 11322580
    Abstract: In some embodiments, the present disclosure relates to a metal-insulator-metal (MIM) device. The MIM device includes a substrate, and a first and second electrode stacked over the substrate. A dielectric layer is arranged between the first and second electrodes. Further, the MIM device includes a titanium getter layer that is disposed over the substrate and separated from the dielectric layer by the first electrode. The titanium getter layer has a higher getter capacity for hydrogen than the dielectric layer.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yan-Jie Liao
  • Patent number: 11321232
    Abstract: A method for simultaneously accessing a first DRAM device and a second DRAM device includes the steps of: in an active phase, generating a first signal at a first pad, wherein the first signal is provided for the first DRAM device to select a first memory bank group, and the first signal is not for the second DRAM device to select any memory bank group; and generating a second signal at the first pad, wherein the second signal is provided for the first DRAM device to select the first bank group, and the second signal and the first signal correspond to a same digital value.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: May 3, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wen-Wei Lin, Kuan-Chia Huang, Ching-Sheng Cheng
  • Patent number: 11322700
    Abstract: A highly portable and highly browsable light-emitting device is provided. A light-emitting device that is less likely to be broken is provided. The light-emitting device has a strip-like region having high flexibility and a strip-like region having low flexibility that are arranged alternately. In the region having high flexibility, a light-emitting panel and a plurality of spacers overlap with each other. In the region having low flexibility, the light-emitting panel and a support overlap with each other. When the region having high flexibility is bent, the angle between normals of facing planes of the two adjacent spacers changes according to the bending of the light-emitting panel; thus, a neutral plane can be formed in the light-emitting panel or in the vicinity of the light-emitting panel.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: May 3, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaaki Hiroki, Akio Endo
  • Patent number: 11322577
    Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Cheng-Yi Peng, Chien-Hsing Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Patent number: 11322538
    Abstract: The present technology relates to an imaging device, an electronic apparatus, and a method of manufacturing an imaging device capable of thinning a semiconductor on a terminal extraction surface while maintaining a strength of a semiconductor chip. There is provided an imaging device including: a first substrate having a pixel region in which pixels are two-dimensionally arranged, the pixels performing photoelectric conversion of light; and a second substrate in which a through silicon via is formed, in which a dug portion is formed in a back surface of the second substrate opposite to an incident side of light of the second substrate, and a redistribution layer (RDL) connected to a back surface of the first substrate is formed in the dug portion. The present technology can be applied to, for example, a semiconductor package including a semiconductor chip.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: May 3, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Suguru Saito, Nobutoshi Fujii
  • Patent number: 11322498
    Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 3, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 11322428
    Abstract: A semiconductor device package includes a substrate, a first semiconductor die, a conductive via, a first contact pad and a second contact pad. The substrate includes a first surface, and a second surface opposite to the first surface, the substrate defines a cavity through the substrate. The first semiconductor die is disposed in the cavity, wherein the first semiconductor die includes an active surface adjacent to the first surface, and an inactive surface. The conductive via penetrates through the substrate. The first contact pad is exposed from the active surface of the first semiconductor die and adjacent to the first surface of the substrate. The second contact pad is disposed on the first surface of the substrate, wherein the second contact pad is connected to a first end of the conductive via.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 3, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt
  • Patent number: 11324086
    Abstract: The present invention provides a self-adaptive dimming driving system, configured to work with a light-emitting diode (LED) power port, the self-adaptive dimming driving system comprising: a driving circuit, a forward bias voltage detection circuit, and a controller. The driving circuit is connected to the LED power port. The forward bias voltage detection circuit is connected between the LED power port and the driving circuit, Wherein the forward bias voltage detection circuit comprises a test current output module and a voltage feedback module, the test current output module is configured to output a test current to the LED power port, and the voltage feedback module is configured to output a detection signal according to a voltage parameter of the LED power port. The controller receives the detection signal, obtains a barrier potential parameter of an LED lamp according to the detection signal, and switches a power output mode of the driving circuit according to the barrier potential parameter.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: May 3, 2022
    Assignee: IDESYN SEMICONDUCTOR CORP.
    Inventor: Shih-Hsueh Yang
  • Publication number: 20220130776
    Abstract: A semiconductor device package includes an electronic component and a substrate. The electronic component has a first surface and a second surface. The substrate is connected to the first surface of the electronic component through an adhesive layer. The substrate includes a first antenna disposed over the second surface of the electronic components through the adhesive layer.
    Type: Application
    Filed: October 22, 2020
    Publication date: April 28, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU