Abstract: A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: An example method for estimating the angle-of-arrival (AoA) and other parameters of radio frequency (RF) signals that are received by an antenna array comprises: receiving a plurality of radio frequency (RF) signal power measurements by a plurality of antenna elements at a plurality of RF channels; computing, by applying a machine learning model to the plurality of RF signal power measurements, an estimated RF signal parameter value; and outputting the RF signal parameter value.

Abstract: An example device may include an antenna node configured to be coupled to an antenna element. The antenna node may be configured to pass wireless communications over multiple frequency bands. The device may also include multiple signal paths coupled to the antenna node. Each of the multiple signal paths may be configured to carry a signal from a different one of the multiple frequency bands. The device may further include a switch element coupled to the antenna node by the multiple signal paths and an amplifier circuit within the multiple signal paths between the switch element and the antenna node. The amplifier circuit may be configured to amplify the signals carried by the multiple signal paths.

Abstract: An LDMOS device and a method for forming the LDMOS device are provided. The LDMOS device includes: a substrate formed with a source region, a drain region and a drift region; a gate structure; a silicide block layer; a first conductive structure having one end electrically connected with the source region, a second conductive structure having one end electrically connected with the drain region; a first metal interconnecting structure electrically connected with the other end of the first conductive structure, a second metal interconnecting structure electrically connected with the other end of the second conductive structure; a third conductive structure having one end disposed on a surface of the silicide block layer; and a third metal interconnecting structure electrically connected with the other end of the third conductive structure. The LDMOS device has increased breakdown voltage, and reduced on-resistance, and its preparation process is safer and easier to control.

Abstract: A wafer structure, a method for manufacturing the wafer structure, and a chip structure. A front surface of a first chip provided with a photosensitive array is bonded to a front surface of a second chip provided with a logic device. An electrical-connection through-hole is provided on a back surface of the first chip at a pad region. The electrical-connection through-hole runs from the back surface of the first chip, via a top wiring layer in the first chip, to a top wiring layer in the second chip. A pad is provided on the electrical-connection through-hole. Hence, integration of a photosensitive device of a stacked type is achieved. There are advantages of a high integration degree and a simple structure. Transmission efficiency of a device is effectively improved, and complexity of a manufacturing process is reduced.

Abstract: The present application provides an array substrate and a display panel. The array substrate includes a substrate, an active layer, a first metal layer, a second metal layer, a flexible material layer, and a source/drain layer which are disposed in a stack. The active layer forms a source and a drain and connected to a first connection member formed by the second metal layer through a first through-hole. The first connection member is connected to a doped region of the active layer by a second through-hole. An aperture of the first through-hole is greater than an aperture of the second through-hole. Therefore, a technical problem of a poor connection between the source/drain and the active layer is relieved.

Abstract: A solid state image sensor includes a semiconductor substrate where photoelectric conversion regions for converting light into charges are arranged per pixel planarly arranged; an organic photoelectric conversion film laminated at a light irradiated side of the semiconductor substrate via an insulation film and formed at the regions where the pixels are formed; a lower electrode formed at and in contact with the organic photoelectric conversion film at a semiconductor substrate side; a first upper electrode laminated at a light irradiated side of the organic photoelectric conversion film and formed such that ends of the first upper electrode are substantially conform with ends of the organic photoelectric conversion film when the solid state image sensor is planarly viewed; and a film stress suppressor for suppressing an effect of a film stress on the organic photoelectric conversion film, the film stress being generated on the first upper electrode.

Abstract: A highly visible display device is provided. The display device includes a transistor, a first conductive layer, a second conductive layer, and a third conductive layer. The channel width of the transistor is greater than or equal to 30 ?m and less than or equal to 1000 ?m. The transistor includes 2 to 50 semiconductor layers, each of which includes a first region, a second region, and a channel formation region. The channel formation region has a region overlapping overlaps with the first conductive layer. The first region overlaps with the second conductive layer and does not overlap with the first conductive layer. The second region overlaps with the third conductive layer and does not overlap with the first conductive layer. The third conductive layer has a function of transmitting visible light, and the second region and the third conductive layer in a stacked state have a function of transmitting visible light.

Abstract: This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (PRO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (PRST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (VRB1, VPB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

Abstract: A positive electrode active material has a small difference in a crystal structure between the charged state and the discharged state. For example, the crystal structure and volume of the positive electrode active material, which has a layered rock-salt crystal structure in the discharged state and a pseudo-spinel crystal structure in the charged state at a high voltage of approximately 4.6 V, are less likely to be changed by charging and discharging as compared with those of a known positive electrode active material. In order to form the positive electrode active material having the pseudo-spinel crystal structure in the charged state, it is preferable that a halogen source such as a fluorine and a magnesium source be mixed with particles of a composite oxide containing lithium, a transition metal, and oxygen, which is synthesized in advance, and then the mixture be heated at an appropriate temperature for an appropriate time.

Abstract: The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

Abstract: A semiconductor device includes a first source/drain structure, a channel layer, a second source/drain structure, a gate structure and an epitaxial layer. The channel layer is above the first source/drain structure. The second source/drain structure is above the channel layer. The gate structure is on opposite first and second sidewalls of the channel layer when viewed in a first cross-section taken along a first direction. The gate structure is also on a third sidewall of the channel layer but absent from a fourth sidewall of the channel layer when viewed in a second cross-section taken along a second direction different from the first direction. The epitaxial layer is on the fourth sidewall of the channel layer when viewed in the second cross-section and forming a P-N junction with the channel layer.

Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.

Abstract: An image sensor may include an array of image pixels. Control circuitry coupled to the array of pixels may be configured to operate the image pixels in an overflow mode of operation, in which each pixel generates an overflow image signal and a complete image signal from a single exposure time period. The overflow image signals and the complete image signals from the pixels may be used to generate a high dynamic range image. While the floating diffusion region in each pixel is not in use, control circuitry may control that pixel to generate a reference signal at the floating diffusion region indicative of pixel-specific dark signal noise. Processing circuitry may mitigate for dark signal non-uniformity across the pixels by correcting the complete image signals using the reference signal to remove dark signal noise in the complete image signals.

Abstract: A reticle, a reticle container and a method for discharging static charges accumulated on a reticle are provided. The reticle includes a mask substrate, a reflective multilayer (ML) structure, a capping layer, an absorption structure and a conductive material structure. The mask substrate has a front-side surface and a back-side surface. The reflective ML structure is positioned over the front-side surface of mask substrate. The capping layer is positioned over the reflective ML structure. The absorption structure is positioned over the capping layer. The conductive material structure is positioned over a sidewall surface of the mask substrate and a sidewall surface of the absorption structure.

Abstract: A method includes switching a receiver path network of a front-end module to a first matching mode in a receive mode. The method further includes switching a transmitter path network of the front-end module to a first resonance mode in the receive mode. The method further includes switching the transmitter path network to a second matching mode in a transmit mode. The method further includes switching the receiver path network to a second resonance mode in the transmit mode.

Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

Abstract: A wafer structure, a method for manufacturing the same and a chip structure are provided. A first capacitor plate is arranged in a first chip, a second capacitor plate is arranged in a second chip, and the first chip is stacked together via bonding layers with the second chip with a front surface of the first chip facing toward a front surface of the second chip. In this way, a capacitor structure formed by the first capacitor plate, the second capacitor plate and dielectric materials provided therebetween is formed while bonding the first chip and second chip together, and the capacitor plate and the dielectric materials may be formed while forming a device interconnection structure in the chip, such that no additional process is required, thereby improving device integration and process integration.

Abstract: The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.