Abstract: Global shutter imaging pixels may include a charge storage region that receives charge from a respective photodiode. Global shutter imaging pixels may be formed as frontside illuminated imaging pixels or backside illuminated imaging pixels. Shielding charge storage regions from incident light may be important for image sensor performance. To shield charge storage regions in backside illuminated global shutter imaging pixels, shielding structures may be included over the charge storage region. The shielding structures may include backside trench isolation structures, a metal layer formed in a backside trench between backside trench isolation structures, and frontside deep trench isolation structures. The metal layer may have angled portions that reflect light towards the photodiodes.

Abstract: A memory cell array includes a first memory cell arranged in a first row in a first direction and a second memory cell arranged in a second row in the first direction. The first memory cell or the second memory cell includes a set of active regions, a set of gates and a first set of conductive structures. Each of the active regions of the set of active regions is separated from an adjacent active region in the first direction by a first pitch. The set of active regions extends in a second direction. The set of active regions includes a first active region adjacent to a first side of the first memory cell, and a second active region adjacent to a second side of the first memory cell. A length of the first active region is different from a length of the second active region.

Abstract: A semiconductor device may include a first inverter, a second inverter, a first access transistor, and a second access transistor. A drain electrode of the first access transistor or a source electrode of the first access transistor may be electrically connected to both an output terminal of the first inverter and an input terminal the second inverter. The drain electrode of the first access transistor may be asymmetrical to the source electrode of the first access transistor with reference to a gate electrode of the first access transistor. A drain electrode of the second access transistor or a source electrode of the second access transistor may be electrically connected to both an output terminal of the second inverter and an input terminal the first inverter.

Abstract: A laser component includes a housing, a laser chip arranged in the housing, and a conversion element for radiation conversion arranged in the housing wherein the conversion element is irradiatable with laser radiation of the laser chip. A method of producing such a laser component includes providing component parts of the laser component including a laser chip, a conversion element for radiation conversion and housing parts, and assembling the component parts of the laser component such that a housing is provided within which the laser chip and the conversion element are arranged, wherein the conversion element is irradiatable with laser radiation of the laser chip.

Abstract: A data converter and an impedance matching control method are provided. The data converter includes a comparator, a capacitor array as well as a switch and impedance matching circuit. The comparator includes a first input terminal and a second input terminal. The capacitor array includes a plurality of capacitors, and a first end of each capacitor is coupled to the first input terminal or the second input terminal. The switch and impedance matching circuit is coupled to a second end of a target capacitor among the capacitors and configured to couple the second end to a first reference voltage or a second reference voltage according to a control signal and adjust an impedance according to an impedance adjusting signal, in which the impedance is the impedance of the switch and impedance matching circuit. The first reference voltage is different from the second reference voltage.

Abstract: A synchronous rectifier controller includes an exception timer, one or more blanking timers, and control logic. The control logic may detect a beginning of a conduction phase using a current sense signal. In response to detecting the beginning of the conduction phase, the control logic commences the exception timer, commences a first blanking interval, and asserts the drive signal. In response to an OFF condition being detected, the first blanking interval being elapsed, and the exception timer being running, the control logic de-asserts the drive signal and commences a second blanking interval. In response to an ON condition being detected, the second blanking interval being elapsed, and the exception timer being running, the control logic commences a third blanking interval and asserts the drive signal. The control logic may assert and de-assert the drive signal multiple times while the exception timer is running.

Abstract: A method for fabricating a semiconductor structure includes forming a plurality of gate structures on the base substrate with each gate structure including a gate electrode and sidewall spacers on each aide surface of the gate electrode, forming source/drain doped regions in the base substrate on opposite sides of each gate structure, forming a sacrificial layer on side surfaces of each sidewall spacer, and performing a pre-amorphous ion implantation process on the source/drain doped regions using the sacrificial layer as a mask.

Abstract: Source and drain formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, wherein the fin structure include a channel region disposed between a source region and a drain region; forming a gate structure over the channel region of the fin structure; forming a solid phase diffusion (SPD) layer over the source region and the drain region of the fin structure; and performing a microwave annealing (MWA) process to diffuse a dopant from the SPD layer into the source region and the drain region of fin structure. In some implementations, the SPD layer is disposed over the fin structure, such that the dopant diffuses laterally and vertically into the source region and the drain region to form heavily doped source/drain features.

Abstract: A method of operating a memory circuit is disclosed. The memory circuit comprises a primary memory and a cache memory. The primary memory has P access channels of Q bits of channel bandwidth, and the cache memory has P subsets of Q*N memory cells, wherein P and Q are integers greater than 1, and N is a positive integer. The method includes determining, in response to a command for reading first and second data accessible through first and second access channels respectively, if a valid duplication of the first and second data is stored in the cache memory. If yes, the method further includes storing a duplication of Q*n bits of consecutively addressed data from each of the first and second access channels to the cache memory, n being an integer from 1 to N. Otherwise, the method further includes outputting the first and second data from the cache memory.

Abstract: An apparatus for monitoring of an ion beam. The apparatus may include a processor; and a memory unit coupled to the processor, including a display routine, where the display routine operative on the processor to manage monitoring of the ion beam. The display routine may include a measurement processor to receive a plurality of spot beam profiles of the ion beam, the spot beam profiles collected during a fast scan of the ion beam and a slow mechanical scan of a detector, conducted simultaneously with the fast scan. The fast scan may comprise a plurality of scan cycles having a frequency of 10 Hz or greater along a fast scan direction, and the slow mechanical scan being performed in a direction parallel to the fast scan direction. The measurement processor may also send a display signal to display at least one set of information, derived from the plurality of spot beam profiles.

Abstract: A display device with low power consumption is provided. A display device having high visibility regardless of the ambient brightness is provided. The display device includes a light-receiving element, a display element, a first transistor, and a second transistor. One of a source and a drain of the first transistor is electrically connected to one electrode of the light-receiving element. The one of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. The display device has a function of, by turning on the second transistor, changing the gray level of the display element in accordance with the amount of light detected by the light-receiving element.

Abstract: The present disclosure relates to the field of intelligent wearable technologies, and provides a power supply circuit, a power supply circuit generation method, and a power supply circuit control method. The present disclosure provides a power supply circuit, including: a bandgap voltage reference Bandgap, a real-time detection and control module, and an alternate voltage source module, where the real-time detection and control module adjusts an output point voltage of the alternate voltage source module according to an output voltage of the Bandgap; and when the output point voltage of the alternate voltage source module reaches a target voltage, the real-time detection and control module closes the Bandgap and supplies power by using the alternate voltage source module.

Abstract: A voltage regulator includes a first feedback circuit, a second feedback circuit, and a feedback signal adaptive circuit. The first voltage feedback circuit includes an amplifier that is configured to generate a compensation signal according to a feedback signal from an output of the voltage regulator and a reference voltage, while the second voltage feedback circuit includes a comparator that is configured to generate a PWM signal to drive a switch circuit in which the comparator initiates the PWM pulse when the feedback voltage goes lower than the compensation signal and ends the PWM pulse when the sum of the feedback signal and a ramp signal exceeds the sum of the compensation signal and a threshold signal. The feedback signal adaptive circuit modifies the feedback signal according to changes in an input voltage of the voltage regulator and a control signal.

Abstract: The present technology relates to a solid-state imaging apparatus and an electronic apparatus that makes it possible to improve coloration and improve image quality. The solid-state imaging apparatus is formed so that, in a pixel array unit in which combinations of a first pixel corresponding to a color component of a plurality of color components and a second pixel having higher sensitivity to incident light as compared with the first pixel are two-dimensionally arrayed, a first electrical barrier formed between a first photoelectric conversion unit and a first unnecessary electric charge drain unit in the first pixel, and a second electrical barrier formed between a second photoelectric conversion unit and a second unnecessary electric charge drain unit in the second pixel have different heights, respectively. The present technology can be applied to, for example, a CMOS image sensor.

Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.

Abstract: A method for manufacturing a highly reliable semiconductor device is provided. The method includes the steps of: forming an oxide semiconductor film at a first temperature; processing the oxide semiconductor film into an island shape; not performing a process at a temperature higher than the first temperature, but depositing a material to be source and drain electrodes by a sputtering method; processing the material to form the source and drain electrodes; forming a protective insulating film, and then forming a first barrier film; adding excess oxygen or oxygen radicals to the protective insulating film through the first barrier film; performing heat treatment at a second temperature lower than 400° C. to diffuse the excess oxygen or oxygen radicals into the oxide semiconductor film; and removing part of the first barrier film and part of the protective insulating film by wet etching, and then forming a second barrier film.

Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes forming an interlayer dielectric layer on a base substrate; forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to a second opening, the one first opening being between the second opening and the base substrate; forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings; forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer; forming an amorphous silicon layer on the cap layer at least on the bottoms of the first openings; performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-K dielectric; removing the amorphous silicon layer; and forming a metal layer, in the first openings and the second openings.

Abstract: A semiconductor device may include the following elements: a first substrate; a second substrate; a dielectric layer, which may be positioned between the first substrate and the second substrate and may have a hole; a first conductive member, which may be positioned in the dielectric layer; a second conductive member, which may be positioned in the dielectric layer, may be spaced from the first conductive member, and may be positioned closer to the second substrate than the first conductive member; and a third conductive member, which may contact both the first conductive member and the second conductive member through the hole.

Abstract: Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.

Abstract: Various embodiments of the present technology may comprise methods and apparatus to measure a route resistance of a battery. The method and apparatus may comprise utilizing various parameters, such as known resistance characteristics, voltage, and current to calculate the route resistance of the battery. In various embodiments, the route resistance may be used to provide a more accurate estimate of the relative state of charge (RSOC).