Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.

Abstract: To provide a semiconductor device with a high output voltage. A gate of a first transistor is electrically connected to a first terminal through a first capacitor. A gate of a second transistor is electrically connected to a second terminal through a second capacitor. One of a source and a drain of a third transistor is electrically connected to the gate of the first transistor through a third capacitor. One of a source and a drain of a fourth transistor is electrically connected to the gate of the second transistor through a fourth capacitor. The other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor are electrically connected to a high potential power source. A third terminal is electrically connected to one of a source and a drain of the second transistor.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate and the first conductive structure. The semiconductor device structure includes a second conductive structure over the first conductive structure and extending into the first dielectric layer. The second conductive structure is electrically connected to the first conductive structure. The semiconductor device structure includes a cover layer between the second conductive structure and the first dielectric layer. The cover layer surrounds the second conductive structure, the second conductive structure passes through the cover layer and is partially between the cover layer and the first conductive structure, and the cover layer includes a metal oxide.

Abstract: A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an example, of the present disclosure operates in a frequency tracking mode to adjust a frequency of the output signal to be proportional to a frequency of a reference input signal, or, in a phase tracking mode to adjust a phase of the output signal to match any variations in the reference input signal. The ADPLL includes a phase and/or frequency detector that provides an error signal representing a difference, in frequency and/or phase, between the output signal and the reference input signal. The ADPLL monitors a trend of the error signal, such as a positive trend, a negative trend, or a flat trend to provide some examples, and switches among the frequency tracking mode and the phase tracking mode upon detecting a change in the trend of the error signal.

Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

Abstract: A method of manufacturing a semiconductor device includes the step of positioning a patterned mask over a dielectric layer. The dielectric layer comprises a low-temperature cure polyimide. The method further includes the steps of exposing a first surface of the dielectric layer through the patterned mask to an I-line wavelength within an I-line stepper, and developing the dielectric layer to form an opening.

Abstract: To provide a novel light-emitting device, a light-emitting device that emits light of a plurality of colors includes a first light-emitting element and a second light-emitting element. The first light-emitting element includes a first lower electrode, a first light-emitting layer over the first lower electrode, a second light-emitting layer over the first light-emitting layer, and an upper electrode over the second light-emitting layer. The second light-emitting element includes a second lower electrode, the first light-emitting layer over the second lower electrode, the second light-emitting layer over the first light-emitting layer, and the upper electrode over the second light-emitting layer. An emission spectrum of the first light-emitting layer peaks at a longer wavelength than an emission spectrum of the second light-emitting layer.

Abstract: A method for forming a MEMS structure includes forming, on a MEMS substrate, an interconnect structure having conductive lines and a first conductive plug of a semiconductor material, forming an etch stop layer on the interconnect structure, forming a dielectric layer over the etch stop layer, bonding a silicon substrate over the dielectric layer, forming a second and third conductive plugs of the semiconductor material in the silicon substrate, wherein the second conductive plug is configured to be electrically coupled with the first conductive plug and third conductive plug is configured to function as an anti-stiction bump, forming a MEMS device electrically coupled with the second conductive feature, and forming a bonding pad on the silicon substrate and surrounded by the second conductive plug.

Abstract: A method for forming a power semiconductor device is provided. The method includes providing a substrate having a first surface and a second surface; and forming a plurality of trenches in the second surface of the substrate. The method also includes forming a semiconductor pillar in each of the plurality of trenches, wherein the semiconductor pillars and the substrate form a plurality of super junctions of the power semiconductor device for increasing the breakdown voltage of the power semiconductor device and reducing the on-stage voltage of the power semiconductor device; and forming a gate structure on the first surface of the substrate. Further, the method includes forming a plurality of well regions in the first surface of the substrate around the gate structure; and forming a source region in each of the plurality of well regions around the gate structure.

Abstract: A method includes forming a molding compound molding a lower portion of an electrical connector of a wafer therein. The molding compound is at a front surface of the wafer. The molding compound covers a center region of the wafer, and leaves an edge ring of the wafer not covered. An opening is formed to extend from the front surface of the wafer into the wafer, wherein the opening is in the edge ring of the wafer. A backside grinding is performed on the wafer until the opening is revealed through a back surface of the wafer. The method further includes determining a position of a scribe line of the wafer using the opening as an alignment mark, and sawing the wafer from a backside of the wafer by sawing through the scribe line.

Abstract: An apparatus for eliminating impulse interference includes an impulse interference detecting unit, an impulse interference eliminating unit and a control unit. The impulse interference detecting unit detects whether impulse interference exists in an input signal according to a predetermined condition, and generates an impulse interference eliminating request when having detected that the input signal satisfies the predetermined condition. In response to the impulse interference eliminating request, the impulse interference eliminating unit performs an impulse interference eliminating process on the input signal to generate an output signal. According to an output signal quality index associated with the output signal, the control unit selectively adjusts the predetermined condition used for detecting whether the impulse interference exists.

Abstract: An apparatus for a lithography device is provided, which includes a laser-based particle eliminating component and a particle collector. The laser-based particle eliminating component includes a laser emitter and a laser absorbing member. The laser emitter is configured to emit laser beams for irradiating particles in a space near a photomask of the lithography device. The laser absorbing member is disposed opposite to the laser emitter for absorbing the laser beams. The particle collector is configured for collecting the irradiated particles.

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include a fuse array that stores configuration data.

Abstract: A switching power converter is provided with an overvoltage protection circuit that softly switches on a power bus switch during a soft-start period responsive to a device connecting to a data cable for receiving power over a power bus coupled to the power bus switch.

Abstract: A voltage regulator includes a control circuit, a switch circuit, a first over-current protection circuit, and a second over-current protection circuit. The control circuit generates a pulse-width modulation (PWM) signal having a duty cycle proportional to an output voltage of the voltage regulator. The first over-current protection circuit blocks the PWM signal when an over-current condition exists during an off time of the PWM signal until a low-side switch current-sense level in the switch circuit drops below a set current limit level, while the second over-current protection circuit turns off the PWM signal when an over-current condition occurs during an on time of the PWM signal when a ramp adjusted voltage level added to the low-side switch current-sense level exceeds a summed level of the set current limit level and a set threshold.

Abstract: A process of producing a component includes providing a substrate having an electrically conductive surface in the form of an electrically conductive layer; subdividing the layer with the aid of a scratching process into a first electrically autonomous region and a second electrically autonomous region, wherein an electrically insulating region is formed in the electrically conductive layer to electrically separate the electrically autonomous regions; forming an electrical potential difference between the first electrically autonomous region and the second electrically autonomous region; and applying an electrically charged substance or an electrically charged substance mixture onto the first electrically autonomous region and/or the second electrically autonomous region, wherein the electrically autonomous region and/or an amount of the applied electrically charged substance or of the electrically charged substance mixture are adjusted by the electrical potential difference.

Abstract: A secondary battery protection circuit includes a first terminal connected to a power supply path between a secondary battery and a MOS transistor, a second terminal connected to the power supply path between a load and the MOS transistor, a third terminal connected to a gate of the MOS transistor, a fourth terminal connected to a back gate of the MOS transistor, a control circuit that outputs a switch control signal based on a detected abnormal state of the secondary battery, and a switch control circuit including a first switch for connecting the fourth terminal with the first terminal and a second switch for connecting the fourth terminal with the second terminal. At least one of the resistance between the fourth terminal and the first terminal and the resistance between the fourth terminal and the second terminal is greater than the on resistance value of the MOS transistor.

Abstract: In a general aspect, an apparatus can include a first substrate operatively coupled with a second substrate. The apparatus can also include a power supply terminal assembly including a first power supply terminal aligned along a first plane, the first power supply terminal being electrically coupled with the first substrate. The power supply terminal assembly can also include a second power supply terminal aligned along a second plane, the second power supply terminal being electrically coupled with the second substrate. The power supply terminal assembly can further include a power supply terminal frame having an isolation portion disposed between the first power supply terminal and the second power supply terminal and a retention portion disposed around a portion of the first power supply terminal and disposed around a portion of the second power supply terminal.

Abstract: A device includes a metal pad at a surface of an image sensor chip, wherein the image sensor chip includes an image sensor. A stud bump is disposed over, and electrically connected to, the metal pad. The stud bump includes a bump region, and a tail region connected to the bump region. The tail region includes a metal wire portion substantially perpendicular to a top surface of the metal pad. The tail region is short enough to support itself against gravity.

Abstract: A radio frequency interconnect includes a transmitter coupled with an input end of a transmission line, and a receiver coupled with an output end of the transmission line. The transmitter includes a first carrier generator configured to generate a clock recovery signal based on a carrier signal, to output a reference clock signal, and to transmit the clock recovery signal to the receiver. The transmitter also includes a modulator configured to modulate a data packet based on the carrier signal. The transmitter also includes a preamble generator configured to generate and add a preamble to data to generate the data packet. The preamble includes a data sequence associated with the reference clock signal. The transmitter further includes a transmitter output configured to transmit the modulated data packet to the receiver by the transmission line.