Abstract: Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure.

Abstract: Exemplary embodiments for redistribution layers of integrated circuit components are disclosed. The redistribution layers of integrated circuit components of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.

Abstract: An interconnect structure includes a dielectric layer, a conductive feature, a conductive layer, a capping layer, a support layer and an etch stop layer. The conductive feature is disposed in the dielectric layer. A first portion of the conductive layer is disposed over the first conductive feature, and a second portion of the conductive layer is disposed over the dielectric layer. A first portion of the capping layer is in contact with the first portion of the conductive layer, a second portion of the capping layer is in contact with the second portion of the conductive layer, and a third portion of the capping layer is in contact with the dielectric layer. An air gap is defined by the support layer and the capping layer. The etch stop layer is disposed over the second portion of the conductive layer, the second portion of the capping layer and the support layer.

Abstract: The present application discloses a display panel and a display device. A first metal layer includes at least one first signal transmitting portion. An insulating layer includes a protrusion portion covering the first signal transmitting portion. A second metal layer includes at least one second signal transmitting portion. The second signal transmitting portion includes a first sub-portion, a second sub-portion, and a third sub-portion. The second sub-portion and the third sub-portion are respectively connected to two ends of the first sub-portion. A conductive layer includes a bridging portion. An orthographic projection of the second sub-portion on a substrate and an orthographic projection of the third sub-portion on the substrate both fall outside a coverage of an orthographic projection of the protrusion portion on the substrate. Two ends of the bridging portion are electrically connected to the second sub-portion and the third sub-portion respectively.

Abstract: A semiconductor device includes a controller circuit and a signal generating circuit. The controller circuit is coupled to a plurality of memory devices and configured to generate a plurality of chip enable signals. One of the chip enable signals is provided to one of the memory devices, so as to respectively enable the corresponding memory device. The signal generating circuit is disposed outside of the controller circuit and configured to receive the chip enable signals and generate a termination circuit enable signal according to the chip enable signals. The termination circuit enable signal is provided to the memory devices. When a state of any of the chip enable signals is set to an enabled state, a state of the termination circuit enable signal generated by the signal generating circuit is set to an enabled state.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

Abstract: A three-dimensional memory device includes a stacking structure, memory pillars, and conductive pillars. The stacking structure includes stacking layers stacked along a vertical direction, each stacking layer including a gate layer, a gate dielectric layer, and a channel layer. The gate layer, the gate dielectric layer, and the channel layer extend along a horizontal direction, and the gate dielectric layer is disposed between the gate layer and the channel layer. The memory pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. Each memory pillar comprises a first electrode, a second electrode, and a switching layer between the first and second electrodes. The conductive pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. The memory pillars and the conductive pillars are alternately arranged along the horizontal direction.

Abstract: A semiconductor package includes: a first die; a second die stacked on an upper surface of the first die, the second die including a second semiconductor substrate and a second seal ring structure that extends along a perimeter of the second semiconductor substrate; a third die stacked on the upper surface of the first die, the third die including a third semiconductor substrate and a third seal ring structure that extends along a perimeter of the third semiconductor substrate; and a connection circuit that extends through the second seal ring structure and the third seal ring structure, in a lateral direction perpendicular to the stacking direction of the first die and the second die, to electrically connect the second semiconductor substrate and the third semiconductor substrate.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes gate electrodes and first insulation patterns laterally disposed and alternately arranged on a substrate, a gate dielectric layer disposed on the gate electrodes and the first insulation patterns, at least one channel pattern disposed on the gate dielectric layer, source electrodes and drain electrodes laterally disposed and alternately arranged on the channel pattern, and second insulation patterns disposed on the channel pattern between the source and drain electrodes. Besides, from a top view, each of the drain electrodes is overlapped with one of the first insulation patterns.

Abstract: Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a dielectric feature having a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core) and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, a conductive terminal, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The conductive terminal is connected to the redistribution layer. The through via extends through the encapsulant and the redistribution layer to contact the conductive terminal and the second RDL structure.

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

Abstract: A mask includes a reflective layer, an absorption layer and an absorption part. The absorption layer is disposed over the reflective multilayer. The absorption part is disposed in the reflective layer and the absorption layer, wherein an entire top surface of the absorption part is substantially flush with a top surface of the absorption layer.

Abstract: A BJT and methods of forming the same are described. The BJT includes a collector region disposed in a substrate, a lower base structure disposed on the collector region, a first dielectric layer surrounding a bottom portion of the lower base structure, and a second dielectric layer surrounding a top portion of the lower base structure. The first dielectric layer includes a first oxide, the second dielectric layer includes a second oxide, and the first and second oxides have different densities. The BJT further includes an upper base structure disposed on the second dielectric layer and the lower base structure, an emitter region disposed on the lower base structure, a sidewall spacer structure disposed between the emitter region and the upper base structure, and the sidewall spacer structure includes a material different from materials of the first and second dielectric layers.

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device in which first to third conductors are placed over a first oxide; first and second oxide insulators are placed respectively over the second and third conductors; a second oxide is placed in contact with a side surface of the first oxide insulator, a side surface of the second oxide insulator, and a top surface of the first oxide; a first insulator is placed between the first conductor and the second oxide; and the first oxide insulator and the second oxide insulator are not in contact with the first to third conductors, the first insulator, and the first oxide.

Abstract: Provided is a solid-state imaging device capable of enhancing pixel sensitivity and preventing color mixture. A solid-state imaging device includes: a plurality of microlenses that condenses incident light; a plurality of color filters that transmits light of a specific wavelength included in the condensed incident light; a plurality of photoelectric conversion parts on which light having a specific wavelength transmitted through the color filter is incident; and a plurality of waveguide wall parts arranged between the color filters and surrounding the color filter. Then, each of the plurality of waveguide wall parts is formed in a position subjected to pupil correction.

Abstract: A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.

Abstract: A semiconductor device includes a first transistor having a first fin, wherein a base of the first fin is surrounded by a first dielectric material, the first fin having a first fin height measured from the top surface of the first dielectric material to a top surface of the first fin; and a second transistor having a second fin, wherein a base of the second fin is surrounded by a second dielectric material, the second fin having a second fin height measured from a top surface of the second dielectric material to a top surface of the second fin, wherein the first fin height is different from the second fin height.

Abstract: A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a reference layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.