Abstract: A processing device comprises inter alia a monolithic memory accumulator unit, which exposes a virtual memory space to an interconnect bus and comprises a conversion table with translation information to translate requests with virtual addresses into requests with physical addresses. The MMA is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to pass on transaction request(s) to storage locations of an integrated peripheral. A processing device comprises at least one integrated peripheral, IP, with an accessibility adapter unit, AA, which exposes a virtual memory space to the interconnect bus 650 and which comprises a conversion table with translation information. The AA 150 is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to route transaction request(s) to storage locations of the IP.

Abstract: Driver circuits comprise power converters detecting automatically a topology used by the driver circuits. A controller controls a plurality of different types of power converters in accordance to a corresponding plurality of different operation modes. The controller comprises a measurement pin coupled to a first topology resistor of a first power converter of a type from the plurality of different types. The different types of power converters comprise topology resistors of corresponding different resistor values. The controller senses a voltage at the measurement pin wherein the voltage at the measurement pin is indicative of a voltage drop at the first topology resistor. Furthermore, the controller determines a type of the first power converter based on the sensed voltage, and selects an operation mode for controlling the first power converter.

Abstract: An integrated circuit (IC) electromagnetic interference (EMI) filter with electrostatic discharge (ESD) protection incorporating inductor-capacitor (LC) resonance tanks is disclosed. The filter comprises at least one circuit composed of a diode and an inductor connected in series, wherein the diode induces a parasitic capacitance and the circuit is grounded. When a number of the circuit is two, a passive element is coupled between the two inductors and cooperates with them to induce two parasitic capacitances connected with the circuits. When a number of the circuit is one, two diodes respectively connect with the inductor through two passive elements. Each diode can induce a parasitic capacitance. The two passive elements and the inductor can induce a parasitic capacitance connected with the circuit.

Abstract: A system and method is disclosed for adjusting for timing variations between a data signal and an associated data read signal being transmitted from a first chip and received on a second chip.

Abstract: Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: placing a device die having a plurality of metal posts over a release layer, wherein the release layer is over a first carrier; forming a plurality of through-assembly vias (TAVs) over the release layer; forming a dam member between the device die and the plurality of TAVs; molding the device die, the dam member, and the plurality of TAVs in a molding compound; and grinding the molding compound to expose ends of the plurality of metal posts and ends of the plurality of TAVs, wherein a top surface of the molding compound is substantially level with the exposed ends of the plurality of metal posts and exposed ends of the plurality of TAVs.

Abstract: A flexible circuit board, a semiconductor package, and methods of forming the same are provided. The flexible circuit board includes: a base film; an input line pattern, an output line pattern, and a dummy pattern on a first surface of the base film; and a ground pattern on a second surface of the base film and electrically connected with the dummy pattern.

Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm?1 and less than or equal to 0.7 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm?1 and less than or equal to 4.1 nm?1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm?1 and less than or equal to 1.4 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm?1 and less than or equal to 7.1 nm?1.

Abstract: A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a fin structure on a semiconductor substrate and forming a well region in the semiconductor substrate by ion implantation so as to form transistors. The transistors include a pull-up transistor, a transfer gate transistor, and a pull-down transistor of a SRAM cell. The ion implantation is used to adjust threshold voltages of the transistors. Standard threshold voltage (SVt) ion implantation conditions are used to adjust a threshold voltage of the pull-up transistor and a threshold voltage of the transfer gate transistor, and low threshold voltage (LVt) ion implantation conditions are used to adjust a threshold voltage of the pull-down transistor.

Abstract: An integrated circuit design method includes extracting a custom IC design parameter from a configuration file using a design customization module (DCM) and creating an IC design file with a module in a processor design kit (PDK) using the custom IC design parameter.

Abstract: A circuit comprises a first transistor and a second transistor in a strap cell region between a first memory array and a second memory array of a memory device. The first transistor includes a first node connected to a first data line, and a second node connected to a second data line. The first node and the second node of the first transistor are complementary to each other in voltage level. Further, the second transistor includes a first node connected to the second data line, and a second node connected to the first data line. The first node and the second node of the second transistor are complementary to each other in voltage level.

Abstract: A method of detecting a parasitic transistor detecting is provided. The method includes extracting several diodes from a selected area, selecting at least one diode pair from the diodes in accordance with signals connected to the diodes, and filtering the at least one diode pair in accordance with a threshold distance to determine whether at least one parasitic transistor is obtained.

Abstract: Methods and systems are disclosed for imminent read failure detection using high/low read voltage levels. In certain embodiments, data stored within an array of non-volatile memory (NVM) cells is checked using read voltage levels below and above a normal read voltage level. An imminent read failure is then indicated if errors are detected within the same address for both voltage checks. Further, data stored can be checked using read voltage levels that are incrementally decreased below and incrementally increased above a normal read voltage level. An imminent read failure is then indicated if read errors are detected within the same address for both voltage sweeps and if high/low read voltage levels triggering faults differ by less than a predetermined threshold value. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.

Abstract: A match-in-place-type compare operation utilizes a string of Magnetic Tunnel Junction (MTJ) elements including storage layers and sense layers having different anti-ferromagnetic structures respectively having higher and lower blocking temperatures. Confidential data is written into the storage layers of the MTJ elements by heating the elements above the higher blocking temperature, and then orienting the storage and sense layers in first storage magnetization directions using field lines. The elements are then cooled to an intermediate temperature between the higher and lower blocking temperatures, and the field lines are turned off, setting the sense layers to preliminary storage magnetization directions opposite to the first directions. During a pre-compare phase, an input logic pattern is written into the sense layers by heating to the intermediate temperature.

Abstract: A low-power protective circuit includes a detection unit that intermittently detects a voltage across a secondary battery; a battery management unit that includes a buffer memory device and a processor and determines, based on a value of the voltage, whether the secondary battery needs to be charged; a switch circuit that establishes or breaks electrical continuity between a host system and the secondary battery; a switch control unit that turns on or off the switch circuit in accordance with the judgment made by the battery management unit; a switch that controls supply of power supply voltage from the secondary battery to the battery management unit; and a power controller that intermittently stops supply of the power supply voltage to the battery management unit by turning off the switch.

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Abstract: In one aspect, a system for depositing a layer on a substrate is provided. The system includes a processing chamber, a gas injecting port, a gas distribution plate, and a plug. The gas injecting port is disposed upstream from the processing chamber. The gas distribution plate is disposed between the gas injecting port and the processing chamber, and includes an elongate planar body and an array of holes therein. The plug is sized to be received within one of the holes, and includes an orifice therethrough for permitting the passage of gas. The plug is capable of being removably secured to the gas distribution plate within one of the holes.

Abstract: Embodiments of a symmetric multi-processing (SMP) system can provide full affinity of a connection to a core processor when desired, even when ingress packet distribution, protocol processing layer and applications may autonomously process packets on different cores of the SMP system. In an illustrative embodiment, the SMP system can include a server application that is configured to create a plurality of tasks and bind the plurality of tasks to a plurality of core processors. One or more of the plurality of tasks are configured to create a corresponding listening endpoint socket, bind and listen on a protocol address that is common to the plurality of tasks.

Abstract: A memory device including a ferroelectric memory array is described. In one embodiment, the ferroelectric memory array includes a user memory space. The memory device includes control logic configured to provide external read and write access for a host system to the user memory space upon authentication between the host system and the memory device. The host system accesses the user memory space and communicates with the control logic through address, data and control buses. The memory device further includes memory interface configured to interface between the address, data and control buses and the control logic, and through which the host system communicates with the control logic, and a cipher engine in communication with the control logic and the memory interface, the cipher engine comprising a random number generator and an encryption/decryption block. Other embodiments are also described.

Abstract: Electronic modules with small and flexible interfaces are disclosed. One example electronic module includes a power supply terminal configured to receive power for the electronic module and circuitry configured to carry out various functions. The functions carried out by the electronic module circuitry include simultaneously receiving both of the following via the power supply terminal: a power signal for carrying out a mission mode operation of the electronic module, and a data signal.