Abstract: Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

Abstract: A substrate may be loaded onto a chemical mechanical polishing (CMP) apparatus, which includes a polishing pad and a wafer carrier that holds the substrate. The wafer carrier includes a backside plate, a wafer carrier frame, and at least one optical vertical displacement measurement unit that includes a respective laser source and a respective pixelated image sensor. A total reflection geometry is used to reflect a laser beam off a top surface of the backside plate. A polish rate or a polish thickness of a polished portion of the substrate may be measured at each location underneath at least one reflection point during the CMP process.

Abstract: An embodiment provides a semiconductor device comprising: a semiconductor structure including a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, and a plurality of first recesses and second recesses which extend through the second conductive semiconductor layer and the active layer and are arranged up to one region of the first conductive semiconductor layer, a first electrode disposed inside each of the first recesses and second recesses to be electrically connected to the first conductive semiconductor layer, and a second electrode electrically connected to the second conductive semiconductor layer, wherein the first conductive semiconductor layer, the active layer, the second conductive semiconductor layer include aluminum, and the number of most adjacent recesses in the plurality of second recesses is fewer than that in the plurality of first recesses and the plurality of second recesses include multiple recesses, each having an area larger than that of each

Abstract: Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

Abstract: Embodiments include plating a contact feature in a first opening in a mask layer, the contact feature physically coupled to a contact pad, the contact feature partially filling the first opening. A solder cap is directly plated onto the contact feature in the first opening. The mask layer is then removed to expose an upper surface of a work piece, the contact feature vertically protruding from the work piece. After utilizing the solder cap, etching the solder cap to remove the solder cap from over the contact feature. A first encapsulant is deposited laterally around and over an upper surface of the contact feature. The first encapsulant is planarized to level an upper surface of the first encapsulant with the upper surface of the contact feature.

Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, and source/drain regions in the substrate and on opposite sides of the gate structure. The gate structure includes an interfacial layer, a quasi-antiferroelectric (QAFE) layer over the interfacial layer, and a gate electrode over the QAFE layer. The QAFE layer includes Hf1-xZrxO2, in which x is greater than 0.5 and is lower than 1.

Abstract: A semiconductor structure includes a redistribution structure, topmost and bottom conductive terminals. The redistribution structure includes a topmost pad in a topmost dielectric layer, a topmost under-bump metallization (UBM) pattern directly disposed on the topmost pad and the topmost dielectric layer, a bottommost UBM pad embedded in a bottommost dielectric layer, and a bottommost via laterally covered by the bottommost dielectric layer. Bottom surfaces of the topmost pad and the topmost dielectric layer are substantially coplanar, bottom surfaces of the bottommost UBM pad and the bottommost dielectric layer are substantially coplanar, the bottommost via is disposed on a top surface of the bottommost UBM pad, top surfaces of the bottommost via and the bottommost dielectric layer are substantially coplanar. The topmost conductive terminal lands on a recessed top surface of the topmost UBM pattern, and the bottommost conductive terminal lands on the planar bottom surface of the bottommost UBM.

Abstract: A semiconductor device that inhibits deterioration of a secondary battery is provided. The semiconductor device includes a secondary battery module and a first circuit. The secondary battery module includes a secondary battery and a sensor. The first circuit includes a variable resistor. The sensor has a function of measuring a temperature of the secondary battery. The first circuit has a function of judging the charge voltage of the secondary battery and outputting a first result; a function of judging the temperature of the secondary battery measured by the sensor and outputting a second result; a function of determining the magnitude of the variable resistor on the basis of the first result and the second result; a function of discharging the charge voltage through the variable resistor; and a function of stopping discharge when the charge voltage reaches a specified voltage.

Abstract: A photodetection device according to the present disclosure includes: a first pixel that is configured to generate a first pixel signal; a reference signal generator that is configured to generate a reference signal; and a first comparator including a first power supply circuit and a first comparison circuit, the first power supply circuit configured to generate a first power supply voltage on the basis of a power supply voltage supplied from a first power supply node and a bias voltage and configured to output the first power supply voltage from an output terminal, and the first comparison circuit configured to operate on the basis of the first power supply voltage and configured to perform a comparison operation on the basis of the first pixel signal and the reference signal.

Abstract: A load, a transistor which controls a current value supplied to the load, a capacitor, a power supply line, and first to third switches are provided. After a threshold voltage of the transistor is held by the capacitor, a potential in accordance with a video signal is inputted and a voltage that is the sum of the threshold voltage and the potential is held. Accordingly, variation in current value caused by variation in threshold voltage of the transistor can be suppressed. Therefore, a desired current can be supplied to a load such as a light emitting element. In addition, a display device with a high duty ratio can be provided by changing a potential of the power supply line.

Abstract: A semiconductor package includes a first die, a second die, an encapsulant, a first inductor and a second inductor. The second die is stacked on the first die along a first direction. The encapsulant encapsulates the second die over the first die. The first inductor is disposed in the encapsulant and has a first spiral structure, wherein the first spiral structure has a plurality of first coils around a first axis, and the first axis is substantially perpendicular to the first direction. The second inductor is disposed in the encapsulant and having a second spiral structure, wherein the first inductor and the second inductor are disposed at opposite sides of the second die.

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

Abstract: To provide an image display device capable of remediation of color breakup, and an electronic device including the image display device. An image display device includes: a first display panel whose transmittance or reflectance of light is controlled on the basis of a first video signal; a second display panel whose transmittance or reflectance of light is controlled on the basis of a second video signal; a light irradiation unit configured to irradiate the first display panel with color light according to the first video signal for driving the first display panel, and to irradiate the second display panel with color light according to the second video signal for driving the second display panel; and a control unit configured to generate the first video signal corresponding to first color light that is one among red color light, green color light, and blue color light, and generate the second video signal that causes emission of second color light that brings the first color light close to white light.

Abstract: An electronic device includes a receiving unit, a signal processing unit, a transmitting unit, and an audio timing unit. The receiving unit receives audio data and first video data. The signal processing unit generates second video data and a pixel clock signal for playing the second video data according to the first video data. The transmitting unit transmits the second video data, the audio data, the pixel clock signal, and a cycle time stamp (CTS) to a receiver. The audio timing unit generates an internal reference signal adjusts a frequency of the internal reference signal according to a receiving speed of the audio data, and generates the CTS according to the internal reference signal and the pixel clock signal so that the receiver can generate an audio clock signal for playing the audio data according to the pixel clock signal and the CTS.

Abstract: The present embodiments disclose a pixel driving circuit.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: The present technology relates to an imaging device and an electronic device that enable construction of an imaging device that outputs information required by a user with a small size. A single-chip imaging device includes: an imaging unit in which a plurality of pixels is arranged two-dimensionally and that captures an image; a signal processing unit that performs signal processing using a captured image output from the imaging unit; an output I/F that outputs a signal processing result of the signal processing and the captured image to an outside; and an output control unit that performs output control of selectively outputting the signal processing result of the signal processing and the captured image from the output I/F to the outside. The present technology can be applied to, for example, an imaging device that captures an image.