Abstract: A system and method for formulating a sequential equivalency problem for fault (non)propagation with minimal circuit logic duplication by leveraging information about the location and nature of a fault. The system and method further apply formal checking to safety diagnoses and efficiently models simple and complex transient faults.

Abstract: A safety analysis method is based on a safety-specific design structural analysis and cone of influence (COI) that does not require fault simulation. The method for performing a safety analysis of an integrated circuit based on a safety-specific design structural analysis and cone of influence comprises generating with a processor a computed set of basic design elements by intersecting two transitive cones of influence, wherein a first cone of influence is a transitive fanin cone of influence starting from a TO element and a second cone of influence is a transitive fanout cone of influence starting from a FROM element.

Abstract: A method of checking equivalence between a first design comprising a shift register logic SRL chain and a second design comprising a memory block. The method comprises identifying an inductive invariant to replace the SRL chain or the memory block, and replacing the SRL chain and the memory block by a set of constraints, wherein the set of constraints state that the SRL chain and the memory block are equivalent for the checking of equivalence between the first design and the second design.

Abstract: A computer implemented method of selecting a prover among a plurality of provers for a design to be verified. The method comprises collecting, by a data module, raw data relating to the design, and extracting from the raw data a plurality of input features, transforming, by a transformer module, the plurality of input features, wherein transforming the plurality of features comprises applying a linear regression to the plurality of features, classifying using a classification module, the provers from the plurality of provers, in which the classification module is adapted to predict a best prover being the prover which solves a property faster than the remaining provers of the plurality of provers, selecting one or more provers based on the results of the classification.

Abstract: A method for formal verification of a digital circuit using a cloud-based verification engine. The method comprises extracting a proof problem from a design of a digital circuit with a local processor, reducing said proof problem to proof relevant data, encrypting said reduced proof problem, transmitting said encrypted reduced proof problem to a remote server, decrypting said encrypted reduced proof problem at said remote server, storing said reduced proof problem in a memory at said remote server, running a proof on said reduced proof problem at said remote server to generate a proof result; encrypting said proof result at said remote server; transmitting said encrypted proof result to said local processor; decrypting said encrypted proof result at said local processor; and reconstructing a verification result of said digital circuit design at said local processor using said decrypted proof result.

Abstract: A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.

Abstract: A method for formal verification of a digital circuit using a cloud-based verification engine. The method comprises extracting a proof problem from a design of a digital circuit with a local processor, reducing said proof problem to proof relevant data, encrypting said reduced proof problem, transmitting said encrypted reduced proof problem to a remote server, decrypting said encrypted reduced proof problem at said remote server, storing said reduced proof problem in a memory at said remote server, running a proof on said reduced proof problem at said remote server to generate a proof result; encrypting said proof result at said remote server; transmitting said encrypted proof result to said local processor; decrypting said encrypted proof result at said local processor; and reconstructing a verification result of said digital circuit design at said local processor using said decrypted proof result.

Abstract: A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.

Abstract: A method for formally verifying the equivalence of an architecture description with an implementation description. The method comprises the steps of reading an implementation description, reading an architecture description, demonstrating that during execution of a same program with same initial values an architecture sequence of data transfers described by the architecture description is mappable to an implementation sequence of data transfers implemented by the implementation description, such that the mapping is bijective and ensures that the temporal order of the architecture sequence of data transfers corresponds to the temporal order of the implementation sequence of data transfers, and outputting a result of the verification of the equivalence of the architecture description with the implementation description.

Abstract: A method is specified for determining the quality of a quantity of properties describing a machine, including a step for determining the existence of at least one sub-quantity of interrelated properties (P0, P1, . . . Pn) of the form Pi=(forall t. Ai(t)=>Zi(t)), wherein Ai(t) present an initial state and Zi(t) a target state for a corresponding property and at least one initial state Ai is dependant on internal signals and including a step for checking whether at least one aspect of the input/output behavior of the machine described by the properties, which cannot be derived from an individual property Pi, is described to such an accurate extent that one property Q exists, which represents this aspect without being dependant on the internal signals. The procedure is capable of providing a measurement and can particularly be used in the verification and specification of circuits.

Abstract: The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second step of indicating at least one exception for the logic circuit; a third step of introducing one or more potential malfunctions of the logic circuit related to the one or more exceptions into the representation of the logic circuit to produce a modified representation of the logic circuit; a fourth step of determining whether functional behavior of the modified representation of the logic circuit differs from functional behavior of the first representation of the logic circuit; and a fifth step of reporting a result relating to the difference in the functional behavior of the modified representation of the logic circuit from the functional behavior of the initial representation of the logic circuit.

Abstract: For the verification of digital circuits, which can have multiplier structures in particular, an equivalence test between the digital circuit and a reference description of this digital circuit is proposed, in such a way that firstly for the multiplier structures implemented in the digital circuit the realized implementation alternative of several pre-defined different implementation alternatives is determined in each case and inserted into the reference description in place of the respective multiplication function, in order subsequently to execute the equivalence test with the reference description changed thereby. In this way, the structural equivalence between the reference description and the digital circuit to be verified can be substantially increased, which speeds up the verification process overall.

Abstract: A system and method for locating circuit deviations or circuit faults in a circuit in respect of a reference circuit. The circuit and the reference circuit are respectively describable by signal-flow graphs, the signal-flow graphs being composed of a multiplicity of interconnected function blocks. The function blocks of the circuit are first assigned to corresponding function blocks of the reference circuit. There are then ascertained those function blocks of the circuit and of the reference circuit for which assignment has not been possible, and which have disposed upstream in the signal flow at least one function block for which assignment has been possible. The result is a boundary between an assigned and a non-assigned region of the circuit and the reference circuit, respectively. A representation of the circuit and reference circuit is preferably produced in which the regions corresponding to the non-assigned function blocks are highlighted.

Abstract: When designing digital circuits, the specification of the circuit is used to formulate properties and to check the applicability thereof using a model of the circuit. A verifier is employed and uses the model to determine whether a property is applicable by seeking a counterexample to which the property does not apply. Any counterexample appearing is evaluated to determine whether it is caused by a defective model or whether it should have been avoided by reformulating the property within the scope of the specification. Which exact part of the property led to the counterexample is determined when one appears. If a plurality of times is possible for a part of the property, the instant(s) at which specific events in the parts of the property lead to the counterexample is determined. A developer can evaluate the counterexample much more quickly using this information, so the development process can be accelerated.

Abstract: The invention creates a technology for validating simulation results. The quickly growing number of components in modern complex systems often necessitates the introduction of abstractions, that render said systems manageable. However the abstractions, which often are based simplified assumptions, may impair the simulation results. The automatic post-processing method according to the invention safeguards the validity of the result. In most cases this can be reached, without restoring the complete description, which generally is too complex. The method, which is described for the validation of calculated counter-examples in an equivalence comparison of digital circuits can be used in all other applications, that allow for an analagous formalization of the abstraction step.

Abstract: A method and an apparatus for verification of arithmetic digital circuits is disclosed, wherein a first circuit, called a specification, is compared for equivalence with a further circuit called an implementation, with equivalence occurring when and only when the specification and implementation always produce the same output signals for the same input signals. The gate level description of the specification and implementation are converted to a network of elementary arithmetic 1-bit operations (XOR, half-adders, full adders) and the equivalence of the specification and implementation is identified in that a comparison of the resultant networks from elementary arithmetic 1-bit operations is carried out directly.

Abstract: The invention permits a comparison of two technical systems, which according to conventional opinion is not possible to carry out, based on a substantially simpler, technically achievable comparison, in which part systems of one or both systems are specifically replaced. The replacements are performed in a controlled manner by monitoring a replacement condition with constraints. The monitoring of the replacement condition and the generation and monitoring of the necessary constraints occur automatically. A comparison of both systems can thus be carried out based on the replacement of the part systems without introducing a loss of precision in the comparison.