Abstract: A page in a memory is sectioned into a plurality of pagelets of sizes smaller than the page thus speeding up data transfers. The pagelets in the page are used to store, transport and process data, wherein individual pagelets are transferred between-a memory and secondary storage in any order such that there is a reduction in the effective latency of the transfer of critical chunks of data. A pagelet translation lookaside buffer that handles translations for pages of different sizes and/or pages having pagelets is used to cache frequently used translations. A critical pagelet determiner is used to indicate the critical pagelet involved in a transaction. Pagelets of a page share one entry in a page table that also includes a virtual to physical translation. Pagelet validity and dirty indicators are maintained to determine pagelet eviction, writeback and fetch actions in accordance with pagelet handling policies.

Abstract: This invention discloses a novel paradigm, method and apparatus for Matrix Computing which include a novel machine architecture with an embedded storage space for holding matrices and arrays for computing which can be accessed by its columns or by its rows or both concurrently. A large capacity multi length instruction set with instructions and methods to load, store and compute with these matrices and arrays are also disclosed; a method and apparatus to secure, share, lock and unlock this embedded space for matrices under the control of an Operating System or a Virtual Machine Monitor by a plurality of threads and processes are also disclosed. A novel method and apparatus to handle immediate operands used by Immediate Instructions are also disclosed. The structure of the instructions with some key fields and a method for determining instruction length easily are also disclosed.