Patents Assigned to Open-Silicon Inc.
  • Patent number: 9960909
    Abstract: A system for performing hashing includes a controller for controlling the system and for providing a clock signal; an array of integrated circuits; in each integrated circuit, a plurality of cores for performing hashing; and in each core, a plurality of data expanders and data compressors, the data expanders and the data compressors having pipelined circuitry so that two iterations of a hashing loop are performed for each cycle of the clock signal. A method for performing hashing, includes controlling a system having an array of integrated circuits with a clock signal; performing hashing in a plurality of cores in each integrated circuit; and performing for each cycle of the clock signal, in each core, a plurality of data expansion and data compression operations, using pipelined circuitry so that two iterations of a hashing loop are performed for each cycle of the clock signal.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: May 1, 2018
    Assignee: OPEN-SILICON INC.
    Inventors: Vasan Karighattam, Devendra Godbole
  • Patent number: 8413006
    Abstract: A method and system are provided to detect and correct errors in the Interlaken block code overhead bits. Specifically, a method is provided for determining the original transmitted information with a very high probability of correct interpretation. These approaches can also characterized by their minimal complexity. Further, such a method can operate on the received information in a manner that does not require consideration of special cases. Also, the method does not require the source to send any extra information or alter its current behavior in any way. Thus, the approaches described herein are compatible with all existing Interlaken sources and can provide immediate benefits.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: April 2, 2013
    Assignees: PMC-Sierra, Inc., Open-Silicon, Inc.
    Inventors: Winston Ki-Cheong Mok, Steven Scott Gorshe, Matthew David Weber
  • Patent number: 7941776
    Abstract: A closed-loop IC design optimization process by automatically or manually creating design-specific cells with desired characteristics (e.g., performance, area, power, noise, etc.), which will be then implemented as a standard cell (also known hereafter as metacell), from a set of post-layout patterns. A post-layout pattern represents a part or whole of a standard cell and contains information regarding the pattern including, but not limited to, layout, timing, area, power and noise. As the metacells are created from post-layout patterns, the inaccuracies of prior dynamic library techniques are easily avoided. Such metacells, being design-specific, are optimized to satisfy the constraints imposed by the design context, thus bringing the powerful design-specific customization to standard cell-based design methodology.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: May 10, 2011
    Assignee: Open-Silicon Inc.
    Inventors: Purnabha Majumder, Balakrishna Kumthekar, Nimish Rameshbhai Shah, John Mowchenko, Pramit Anikumar Chavda, Yoshihisa Kojima, Hiroaki Yoshida, Vamsi Boppana
  • Patent number: 7805648
    Abstract: There is provided a method that includes, (a) determining a first clock frequency for shifting a first section of a scan pattern set through a path in a digital circuit such that a first power dissipated by the digital circuit while shifting the first section does not exceed a power limit, (b) determining a second clock frequency for shifting a second section of the scan pattern set through the path such that a second power dissipated by the digital circuit while shifting the second section does not exceed the power limit, (c) shifting the first section through the path at the first clock frequency, and (d) shifting the second section through the path at the second clock frequency, where first and second clock frequencies are different from one another. There is also provided a system that performs the method.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: September 28, 2010
    Assignee: Open-Silicon Inc.
    Inventor: Aditya Ramachandran
  • Publication number: 20090254787
    Abstract: There is provided a method that includes, (a) determining a first clock frequency for shifting a first section of a scan pattern set through a path in a digital circuit such that a first power dissipated by the digital circuit while shifting the first section does not exceed a power limit, (b) determining a second clock frequency for shifting a second section of the scan pattern set through the path such that a second power dissipated by the digital circuit while shifting the second section does not exceed the power limit, (c) shifting the first section through the path at the first clock frequency, and (d) shifting the second section through the path at the second clock frequency, where first and second clock frequencies are different from one another. There is also provided a system that performs the method.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 8, 2009
    Applicant: Open-Silicon, Inc.
    Inventor: Aditya Ramachandran