Patents Assigned to Optimal Plus Ltd
  • Publication number: 20240170348
    Abstract: A method of testing semiconductor wafers includes receiving a wafer bin map for a semiconductor wafer, wherein the wafer bin map includes a plurality of points corresponding to a plurality of defective dies fabricated on the semiconductor wafer, identifying a cluster of points in the wafer bin map from the plurality of points, and generating a filtered bin map using the cluster of points. The method also includes extracting a set of features for the filtered bin map, wherein the set of features comprises a set of global features common to the semiconductor wafer and a set of cluster features specific to the filtered bin map, executing a trained machine learning model using the set of features as inputs to generate a pattern classification, and determining, based on the pattern classification, that the semiconductor wafer includes a pattern of defective dies caused by a defective manufacturing process.
    Type: Application
    Filed: November 20, 2023
    Publication date: May 23, 2024
    Applicant: Optimal Plus Ltd.
    Inventors: Ofir Suranyi, Miriam Horovicz, Alberto Alexis Jeno
  • Patent number: 11919046
    Abstract: A method of sorting an electronic device includes receiving first data generated by a test tool that is performing a test operation on the electronic device according to a test program, and a provisional binning assignment for the electronic device determined from the first data. The method also includes defining a permanent binning assignment for the electronic device based at least in part on applying a first algorithm and a second algorithm to the first data, the first algorithm and the second algorithm being different. The method further includes outputting the permanent binning assignment so that after the test operation is completed, the electronic device is removed from the test tool and placed in one of a plurality of bins according to the permanent binning assignment.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: March 5, 2024
    Assignee: Optimal Plus Ltd.
    Inventors: Reed Linde, Gill Balog
  • Patent number: 11852684
    Abstract: A method of identifying defects in an electronic assembly, comprising, by a processing unit, obtaining a grid of nodes representative of a location of electronic units of an electronic assembly, wherein each node is neighboured by at most eight other nodes, wherein a first plurality of nodes represents failed electronic units according to at least one test criterion, and a second plurality of nodes represents passing electronic units according to the least one first test criterion, based on the grid, determining at least one first and second straight lines, and attempting to connect the first and second straight lines into a new line, wherein if at least one node from the new line belongs to the second plurality of nodes, concluding that an electronic unit represented by the node on the grid is a failed electronic unit, thereby facilitating identification of a failed electronic unit on the substrate.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: December 26, 2023
    Assignee: Optimal Plus Ltd.
    Inventors: Leonid Gurov, Gal Peled, Dan Sebban, Shaul Teplinsky
  • Patent number: 11775876
    Abstract: A method comprising, by a processing unit and a memory: obtaining a training set of data; dividing sets of data into a plurality of groups, wherein all sets of data for which feature values meet at least one similarity criterion, are in the same group, storing in a reduced training set of data, for each group, at least one aggregated set of data, wherein, for a plurality of the groups, a number of aggregated sets of data is less than a number of the sets of data of the group, wherein the reduced training set of data is suitable to be used in a classification algorithm for determining a relationship between the at least one label and the features of the electronic items, thereby reducing computation complexity when processing the reduced training set of data, compared to processing the training set of data.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: October 3, 2023
    Assignee: Optimal Plus Ltd.
    Inventor: Katsuhiro Shimazu
  • Patent number: 11650250
    Abstract: A method of identifying defects in an electronic assembly, comprising, by a processing unit, obtaining a grid of nodes representative of a location of electronic units of an electronic assembly, wherein each node is neighboured by at most eight other nodes, wherein a first plurality of nodes represents failed electronic units according to at least one test criterion, and a second plurality of nodes represents passing electronic units according to the least one first test criterion, based on the grid, determining at least one first and second straight lines, and attempting to connect the first and second straight lines into a new line, wherein if at least one node from the new line belongs to the second plurality of nodes, concluding that an electronic unit represented by the node on the grid is a failed electronic unit, thereby facilitating identification of a failed electronic unit on the substrate.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: May 16, 2023
    Assignee: Optimal Plus Ltd.
    Inventors: Leonid Gurov, Gal Peled, Dan Sebban, Shaul Teplinsky
  • Publication number: 20230032092
    Abstract: A method for generating a reliability performance model includes developing a reliability prediction machine learning model for predicting reliability performance of a product based on data obtained from manufacturing and testing of the product, and obtaining feature names for the reliability prediction machine learning model and their predictive power values. The feature names may correspond to features from the data obtained from manufacturing and testing of the product. The method may further include extracting a set of feature names corresponding to features having highest predictive power values from the feature names, and generating a reliability performance model using one or more model parameters derived from the set of feature names.
    Type: Application
    Filed: September 30, 2022
    Publication date: February 2, 2023
    Applicants: Optimal Plus Ltd., ANSYS Inc.
    Inventors: Shaul Teplinsky, Dan Sebban, Craig Hillman, Ashok Alagappan
  • Publication number: 20220349930
    Abstract: A method for analyzing device test data includes accessing a core analytics rule that is based on manufacturing data of a plurality of devices. Each of the plurality of devices are produced in one of a plurality of manufacturing facilities and are of a same type as a first device being tested on a tester. The method also includes receiving initial test results of a plurality of other devices of a same type tested at a testing facility, generating, based on the initial test results, an edge analytics rule, modifying the core analytics rule based on the edge analytics rule, wherein the modified core analytics rule including modified binning limits, applying the modified core analytics rule to testing data obtained by testing the first device, and determining, based on applying the modified core analytics rule, that the first device is an outlier with respect to the modified binning limits.
    Type: Application
    Filed: July 12, 2022
    Publication date: November 3, 2022
    Applicant: Optimal Plus Ltd.
    Inventors: Shaul Teplinsky, Arie Peltz, Dan Sebban
  • Publication number: 20220184665
    Abstract: A method of sorting an electronic device includes receiving first data generated by a test tool that is performing a test operation on the electronic device according to a test program, and a provisional binning assignment for the electronic device determined from the first data. The method also includes defining a permanent binning assignment for the electronic device based at least in part on applying a first algorithm and a second algorithm to the first data, the first algorithm and the second algorithm being different. The method further includes outputting the permanent binning assignment so that after the test operation is completed, the electronic device is removed from the test tool and placed in one of a plurality of bins according to the permanent binning assignment.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 16, 2022
    Applicant: Optimal Plus Ltd.
    Inventors: Reed Linde, Gill Balog
  • Patent number: 11235355
    Abstract: Systems and methods for sorting an electronic device undergoing a final test operation in accordance with a test program, into one of a plurality of bins. In one embodiment, an evaluator defines the binning of the electronic device while the device is still socketed, and the defined binning may or may not concur with the binning assigned by the test program.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: February 1, 2022
    Assignee: Optimal Plus Ltd.
    Inventors: Reed Linde, Gill Balog
  • Patent number: 9529036
    Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: December 27, 2016
    Assignee: Optimal Plus Ltd.
    Inventors: Gil Balog, Reed Linde, Avi Golan
  • Patent number: 8872538
    Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 28, 2014
    Assignee: Optimal Plus Ltd.
    Inventors: Gil Balog, Reed Linde, Avi Golan
  • Patent number: 8838408
    Abstract: Systems and methods for deciding whether or not to indicate misalignment. In some examples, an analysis of parametric data relating to tests sensitive to misalignment is performed in order to determine which data is incongruous and to identify corresponding probes or socket contacts as suspected misaligned. In some examples, additionally or alternatively, a spatial analysis quantifies the placement of a set of identified suspected misaligned probes, which were identified from pass/fail test data and/or parametric test data, with respect to a contiguous or non-contiguous area on one or more wafers.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: September 16, 2014
    Assignee: Optimal Plus Ltd
    Inventors: Reed Linde, Dan Glotter, Alexander Chufarovsky, Leonid Gurov
  • Patent number: 8781773
    Abstract: Methods, systems, computer-program products and program-storage devices for determining whether or not to perform an action based at least partly on an estimated maximum test-range. One method comprises: attaining results generated from a parametric test on semiconductor devices included in a control set; selecting from the semiconductor devices at least one extreme subset including at least one of a high-scoring subset and a low-scoring subset; plotting at least results of the at least one extreme subset; fitting a plurality of curves to a plurality of subsets of the results; extending the curves to the zero-probability axis for the low-scoring subset or the one-probability axis for the high-scoring subset to define a corresponding plurality of intersection points; defining an estimated maximum test range based on at least one of the intersection points; and determining whether or not to perform an action based at least partly on the estimated maximum test range.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: July 15, 2014
    Assignee: Optimal Plus Ltd
    Inventors: Leonid Gurov, Alexander Chufarovsky, Gil Balog, Reed Linde