Abstract: Architecture for efficient processing of the evolving OTN transmission technology, standardized under ITU-T G.709, in conjunction with existing and emerging SONET/SDH protocol signals, standardized under ANSI T1.105/ITU-T G.707. The new architecture allows processing the SONET/SDH signals, and/or OTN signals, and/or SONET/SDH mapped into OTN signals more efficiently. The architecture further allows processing and multiplexing of lower order signals into a higher order signal such as quad OC-192 into OC-768 or quad OC-192 into OPU3 and OTU3. This architecture uses an embedded processor to process some of the signals' overhead in software, contributing to an additional level of flexibility in the processing. This architecture enables customization and allowing for future standard updates and upgrades. The architecture can be upgraded to SONET OC-3072, SDH STM-1024 and OTU4, which currently are not standardized. The architecture can also be used for the implementation of SONET OC-192 with OTN OTU2.

Abstract: Architecture for efficient processing of the evolving OTN transmission technology, standardized under ITU-T G.709, in conjunction with existing and emerging SONET/SDH protocol signals, standardized under ANSI T1.105/ITU-T G.707. The new architecture allows processing the SONET/SDH signals, and/or OTN signals, and/or SONET/SDH mapped into OTN signals more efficiently. The architecture further allows processing and multiplexing of lower order signals into a higher order signal such as quad OC-192 into OC-768 or quad OC-192 into OPU3 and OTU3. This architecture uses an embedded processor to process some of the signals' overhead in software, contributing to an additional level of flexibility in the processing. This architecture enables customization and allowing for future standard updates and upgrades. The architecture can be upgraded to SONET OC-3072, SDH STM-1024 and OTU4, which currently are not standardized. The architecture can also be used for the implementation of SONET OC-192 with OTN OTU2.

Abstract: An apparatus and a method for accelerating Cyclic Redundancy Check (CRC) calculations. The apparatus includes a CRC circuit and an accelerator for accelerating the computation of the CRC code so that the CRC code is outputted immediately after the last bit of the input data stream is inserted to the CRC machine, thereby reducing the time required to compute the CRC calculation. The apparatus accelerates the CRC calculation by eliminating the need to append zeros to the input data stream.

Abstract: A method for mapping and multiplexing of constant bit rate (CBR) signals into optical transport network (OTN) frames is provided. The method, in addition, enables the transportation of data from a plurality of SONET/SDH clients through a single OTN frame. The preferred method thereby enables efficient adoption of SONET/SDH legacy equipment by OTN networks.

Abstract: An apparatus and method for detection of periodic patterns in digital high rate transmission systems. The apparatus generates a synthetic data stream and compares, in parallel, a sample of the generated data to a sample of an input data stream. If the number of mismatches between both sets of data is equal to or below a defined threshold, then a detection signal is asserted. The provided apparatus may be configured to detect any type of pattern.

Abstract: A method and system for generating a pseudo-random bit series based on a given polynomial of order N, for M parallel communication lines using a machine comprising: N flip-flop machines and logic circuit. The flip-flop machines is initialized according to a given series of N bits. The logic circuit calculates a series of the next M+N tits using the N flip flop machines as function of the current N bit series wherein the function is based on two pre-generated equations. These equations are generated by recursive calculation of matrix array of order N*M according the given polynomial equation.