Patents Assigned to Optoelectronics Technology Research Corporation
  • Patent number: 5741360
    Abstract: In a method of selectively growing a crystal of a compound semiconductor layer which is composed of gallium and arsenic, a selective growth is selectively carried out on a substrate by using a combination of metallic gallium and a reactive gas, such as trisdimethylminoarsine, which includes a metallic compound of arsenic specified by at least one amine. The combination may includes organometallic gallium, such as trimethylgallium, triethylgallium instead of the metallic gallium. Such a combination serves to selectively deposit the compound semiconductor layer only on an exposed portion uncovered with a mask. Any other compound semiconductor layer may be selectively deposited on the exposed portion. The exposed portion may be composed of GaAs, AlGaAs, or InGaAs.
    Type: Grant
    Filed: August 11, 1995
    Date of Patent: April 21, 1998
    Assignee: Optoelectronics Technology Research Corporation
    Inventors: Shigeo Goto, Yasuhiko Nomura, Yoshitaka Morishita, Seikoh Yoshida, Masahiro Sasaki
  • Patent number: 5656540
    Abstract: On a surface of a p-type GaAs (111)B substrate 11, a mesa groove is formed along a [211]A direction. TDMAAs as a group V material and TMGa as a group III material are supplied at 8.times.10.sup.-3 Pa and 8.times.10.sup.-4 Pa, respectively, to grow n-type GaAs 13 dominantly on a side surface of a mesa 12. Subsequently, the group V material is changed to metal As. As.sub.4 and MAGa are supplied at 5.times.10.sup.-3 Pa and 8.times.10.sup.-4 Pa, respectively, to grow p-type GaAs 14 only on a side surface of the GaAs 13. Then, the group V material is again changed to TDMAAs. TDMAAs and TMGa are supplied both at 8.times.10.sup.-4 Pa to grow p-type GaAs 15.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: August 12, 1997
    Assignee: Optoelectronics Technology Research Corporation
    Inventors: Yasuhiko Nomura, Shigeo Goto, Yoshitaka Morishita
  • Patent number: 5073805
    Abstract: In a semiconductor light emitting device comprising an active layer, a hole barrier layer is formed in contact with a first surface of the active layer to provide a barrier against holes in the active layer. The barrier layer does not provide a barrier against electrons tunnelling therethrough. A low energy band gap layer is formed on the barrier layer to have a conduction band minimum which is lower than the conduction band minimum of the active layer at least in a part adjacent to the barrier layer. First and second electrodes are in ohmic contact with an n-type and a p-type conductivity layers which are formed on the low energy band gap layer and a second surface of the active layer, respectively.
    Type: Grant
    Filed: February 22, 1991
    Date of Patent: December 17, 1991
    Assignee: Optoelectronics Technology Research Corporation
    Inventors: Yoshinori Nomura, Hitoshi Ogata
  • Patent number: 4994140
    Abstract: In a method of processing a compound semiconductor wafer to deposit or form a specific layer on a wafer surface, to partially remove the specific layer to partially expose the wafer surface, and to etch a partially exposed area of the wafer, etching is performed by irradiating an electron beam and a specific gas which may be, for example, chlorine gas, bromine gas, iodine, or their compounds. Portions subjected to irradiation of both the electron beam and the specific gas are etched from the wafer. The specific layer is deposited or formed in the form of an oxide layer on the wafer surface by spraying an oxygen gas onto the wafer surface with light irradiated on the wafer surface. Such an oxide layer may be either an adsorbed molecular layer of the oxygen gas or a chemically reacted layer which results from reaction of the oxygen gas with the wafer by the help of irradiation of the light. Alternatively, the specific layer may be either a sulphide layer or a nitride layer.
    Type: Grant
    Filed: January 10, 1990
    Date of Patent: February 19, 1991
    Assignee: Optoelectronics Technology Research Corporation
    Inventors: Akita Kenzo, Mototaka Taneya, Yoshimasa Sugimoto, Hiroshi Hidaka