Abstract: A method for offloading includes a host channel adapter (HCA) receiving a first work request identifying a queue pair (QP), making a first determination that the QP is a proxy QP, and offloading the first work request to a proxy central processing unit (CPU) based on the first determination and based on the first work request satisfying a filter criterion. The HCA further receives a second work request identifying the QP, processes the second work request without offloading based on the QP being a proxy QP and based on the first work request failing to satisfy the filter criterion. The HCA redirects a first completion for the first work request and a second completion for the second work request to the proxy CPU based on the first determination. The proxy CPU processes the first completion and the second completion in order.

Abstract: Systems and methods for efficient picking of instructions for out-of-order issue and execution in a processor. In one embodiment, a processor comprises a unified pick queue that is dynamically allocated. Each entry is configured to store age and dependency information relative to other decoded instructions. Also, each entry stores a picked field, which when asserted indicates the decoded instruction has already been picked for out-of-order issue and execution. When asserted, a trigger field indicates a result of a corresponding decoded instruction will be available a predetermined number of clock cycles afterward. A younger instruction dependent on a result of an older instruction is ready to be picked before the result of the older instruction is available. In this case, the older instruction has asserted picked and trigger fields.

Abstract: Systems and methods for controlling mobile devices are provided. A Bluetooth signal is received at a mobile device. The Bluetooth signal may include a broadcaster request which is configured to convey a set of desired actions to the wireless handheld device. Once the signal is received, the mobile device is able to determine if each action in the set of desired actions conveyed by the broadcaster request would be allowable on the mobile device. Then, the device performs each of the actions which have been determined to be allowable on the receiving device.

Abstract: A computer readable medium that includes computer readable program code embodied therein. The computer readable medium causes the computer system to receive, by a data link rule enforcer, a packet from a packet source of the packets, and obtain a data link rule applying to a data link. The data link is operatively connected to the packet source, and the data link is associated with a media access control (MAC) address. The computer readable medium further causes the computer system to determine, by the data link rule enforcer, whether the packet complies with the data link rule, and drop, by the data link rule enforcer, the packet when the packet fails to comply with the data link rule.

Abstract: We teach a powerful approach that greatly simplifies the design of non-blocking mechanisms and data structures, in part by, largely separate the issues of correctness and progress. At a high level, our methodology includes designing an “obstruction-free” implementation of the desired mechanism or data structure, which may then be combined with a contention management mechanism whose role is to facilitate the conditions under which progress of the obstruction-free implementation is assured. In general, the contention management mechanism is separable semantically from an obstruction-free concurrent shared/sharable object implementation to which it is/may be applied. In some cases, the contention management mechanism may actually be coded separately from the obstruction-free implementation. We elaborate herein on the notions of obstruction-freedom and contention management, and various possibilities for combining the two.

Abstract: A method is disclosed that uses a non-coherent store instruction to reduce inter-thread communication latency between threads sharing a level one write-through cache. When a thread executes the non-coherent store instruction, the level one cache is immediately updated with the data value. The data value is immediately available to another thread sharing the level-one write-through cache. A computer system having reduced inter-thread communication latency is disclosed. The computer system includes a first plurality of processor cores, each processor core including a second plurality of processing engines sharing a level one write-through cache. The level one caches are connected to a level two cache via a crossbar switch. The computer system further implements a non-coherent store instruction that updates a data value in the level one cache prior to updating the corresponding data value in the level two cache.

Abstract: A system and method for space and time efficient bound calculation is disclosed. The method comprises inserting a plurality of key/value pairs into a “Bloom bounder”, each key/value pair comprising a key and a value. For each pair, the inserting includes calculating a plurality of hash values, each calculated by applying a different one of a plurality of hash functions to the key, and selectively updating one or more data arrays based on the plurality of hash values and the value received key/value pair. A bound may then be determined for a given query key by analyzing information in the one or more data arrays to determine a bound value, such that for every received key/value pair with a key matching the query key, the corresponding value is less than or equal to the bound value.

Abstract: A system for distributing network traffic among direct hardware access datapaths, comprising: a processor; one or more activated PNICs; a host operating system; and a virtual machine (VM). Each activated PNIC sends and receives data packets over a network. Each activated PNIC is configured with a virtual function. The VM includes a VNIC and a virtual link aggregator configured to maintain a list identifying each activated PNIC. Virtual function mappings for the VM associate the VM with virtual functions for the activated PNICs. The virtual link aggregator selects the first activated PNIC for servicing a network connection and determines a virtual function for the first activated PNIC. The VNIC for the first activated PNIC uses the virtual function to directly transfer network traffic for the network connection between the VM and the first activated PNIC.

Abstract: One embodiment of the present invention provides a system that facilitates modifying a platform-independent programming language build tool to aid in the development and testing of smart card applications. The system operates by creating a task in the platform-independent programming language build tool that allows a user to perform functions associated with the development and testing of smart card applications. Next, the system extends the platform-independent programming language build tool interface to include the task so that the task is executable by the user. Note that making the task part of the platform-independent programming language build tool interface reduces the overhead involved in performing functions associated with developing and testing smart card applications.

Abstract: A method for load balancing in a server cluster that includes configuring a load management application to use a load balancing decision function selected from a plurality of load balancing decision functions, receiving a request in the server cluster, selecting a request handler from a plurality of request handlers by the load management application using the load balancing decision function, and transmitting the request to the request handler, wherein the plurality of load balancing decision functions that includes a default load balancing decision function and a custom load balancing decision function.

Abstract: One embodiment of the present invention provides a system that profiles software code to dynamically tune a virtual machine for responsiveness and/or throughput. First, the system profiles software code to track a need for a higher level of responsiveness and/or throughput. The system then gathers statistics for system behavior through the profiling techniques while executing the profiled software code, and uses these statistics to dynamically tune a virtual machine.

Abstract: Indication of uncoverage information allows tests to be tailored to target those uncovered code units with the most potential to increase coverage of a program. A tool examines coverage information of a program to identify code units of the program that were not covered by test data used to exercise the program. The tool also examines structural information (e.g., control flow) for the program to identify those of the uncovered code units that have direct control flow from a corresponding covered code unit (“root level uncovered code units”). The coverage tool then measures potential impact on coverage for each of the root level uncovered code units.

Abstract: In shared-memory computer systems, threads may communicate with one another using shared memory. A receiving thread may poll a message target location repeatedly to detect the delivery of a message. Such polling may cause excessive cache coherency traffic and/or congestion on various system buses and/or other interconnects. A method for inter-processor communication may reduce such bus traffic by reducing the number of reads performed and/or the number of cache coherency messages necessary to pass messages. The method may include a thread reading the value of a message target location once, and determining that this value has been modified by detecting inter-processor messages, such as cache coherence messages, indicative of such modification. In systems that support transactional memory, a thread may use transactional memory primitives to detect the cache coherence messages. This may be done by starting a transaction, reading the target memory location, and spinning until the transaction is aborted.

Abstract: A method for processing a first input/output (I/O) request on a network attached storage (NAS) device that includes receiving the first I/O request from a source by the NAS device, placing the first I/O request in an I/O queue associated with the NAS device, wherein the first I/O request is placed in the I/O queue based on a priority of the first I/O request using a remote storage access protocol, and when the first I/O request is associated with the highest priority in the I/O queue, determining whether a bandwidth associated with the source of the first I/O request is exceeded, processing the first I/O request if the bandwidth associated with the source of the first I/O request is not exceeded, and placing the first I/O request in sleep mode if the bandwidth associated with the source of the first I/O request is exceeded.

Abstract: A system and method for secure generation and distribution of digital encryption keys is disclosed. The system may also be used to protect and distribute other types of secure information, including digital, audio, video, or analog data, or physical objects. The system may include a tamper-respondent secure token device, which may be configured to destroy or disable access to the secure information contained therein in response to attempts to physically or electronically breach the device. Outputs may be provided in a secure manner through various interfaces without using electricity (wires) or electromagnetic radiation. Inputs may be provided in a secure manner, including through the use of a gesture-based input interface. Destruction or disablement of the device and/or its secure contents may be provided upon detection of tamper attempts or upon input of a self-destruct command. Proof of the destruction or disablement of the device or its contents may be provided.

Abstract: Redundant run-time type information is removed from a compiled program. The redundant type information may be unneeded and/or duplicate. Unneeded type information is removed by selecting instances of type information from read only data sections of object files. The entire compiled program is searched for instructions that use the instances. The instances that do not correspond to such instructions are removed from the object files. Duplicate type information is removed by selecting instances of type information from read only data sections of object files. The read only data sections of the other object files in the compiled program are then searched for the selected instances. The selected instances that exist in the read only data sections of the other object files are removed. Redundant type information may be removed from individual object files before concatenation into a single binary file and/or from a single binary file after concatenation.

Abstract: A method for archiving a file that has multiple file parts stored on multiple object storage devices of a computer system includes the steps of saving the file parts on one or more archive devices, allowing one or more changes to be made to the file during the saving step, and applying at least one of the changes made during the saving step to one of the file parts stored on a respective object storage device. Furthermore, the method is performed such that the file parts saved on the one or more archive devices do not include the one or more changes made to the file during the saving step.

Abstract: The present invention provides an interactive graphical user interface (GUI) patch environment for installing a patch on the targeted systems. A system administrator or other authorized user interfaced with a machine may perform the installation of a patch on the machine using a software wizard. Additionally, the Wizard pre-verifies the patch dependencies (pre-installed software) required by the patch and checks the target systems to ensure the target systems possess the requisite dependencies. Once the target systems have been validated and the required dependencies identified on the target systems, the sequencing algorithm sorts patches in correct order before applying patches to the target systems. The user can remove the patch from the pre-validated patch list about to be applied to the target system. The patch dependency is checked before removing the patch from the pre-validated patch list for proper removal order.

Abstract: A system and method for minimizing register spills during compilation. A compiler reallocates spilled variables from stack memory to other available registers. Although a corresponding register file may not have available registers for storage, the compiler identifies available registers in other locations for storage. The compiler identifies available registers in an alternate register file, wherein the alternate register file may be a floating-point register file which is then used for spilled integer variables. Other instruction type combinations between spilled variables and alternate register files are possible. When an available register within the alternate register file is identified, the compiler modifies the program instructions to allocate the corresponding spilled variable to the available register.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide for managing a database. A data store is provided that is distributed over at least two sub data processing systems. A first information in the data store is associated with a first consistency level and a second information in the data store is associated with a second consistency level. At least one of the first consistency level and the second consistency level is selected according to an algorithm.