Abstract: A calculating circuit and a method for generating an output signal representing an output number approximating an N-th root and/or a reciprocal of an input number represented by an input signal are described. The calculating circuit includes a subtractor circuit, an integrator circuit, and a multiplier circuit. The subtractor circuit responsive to a first signal and a feedback signal and configured for generating an error signal representing a difference between the first signal and the feedback signal. The integrator circuit responsive to the error signal and configured for computing the output signal. The multiplier circuit responsive to the output signal and configured for generating a feedback signal.

Abstract: A system for enhancing the reception of a single carrier signal. The single carrier signal includes periodic training signal and data. The system includes a transmitter configured such that L symbols of either the beginning or end of the N symbols of the training signal, where L<N, are duplicated at either the end or the beginning of the training signal, respectively. The system further includes a receiver configured to receive the modified training signal for the calculation of FIR coefficients in a single pass and without the need for least mean square (LMS) methods or the like.

Abstract: A system and method for enhancing the reception of a single carrier signal. The single carrier signal includes periodic training signal and data. The system includes a transmitter configured such that L symbols of either the beginning or end of the N symbols of the training signal, where L<N, are duplicated at either the end or the beginning of the training signal, respectively. The system further includes a receiver configured to receive the modified training signal for the calculation of FIR coefficients in a single pass and without the need for least mean square (LMS) methods or the like.

Abstract: A calculating circuit and a method for generating an output signal representing an output number approximating an N-th root and/or a reciprocal of an input number represented by an input signal are described. The calculating circuit includes a subtractor circuit, an integrator circuit, and a multiplier circuit. The subtractor circuit responsive to a first signal and a feedback signal and configured for generating an error signal representing a difference between the first signal and the feedback signal. The integrator circuit responsive to the error signal and configured for computing the output signal. The multiplier circuit responsive to the output signal and configured for generating a feedback signal.

Abstract: In a composite video signal that contains an image field having vertical synchronization (V.sub.-- Sync) pulses, The V.sub.-- sync pulses include first equalization pulses of E.sub.1 waveforms followed by a serration pulses of S waveforms, T.sub.S -long each, followed by a second equalization pulse of E.sub.2 waveforms, T.sub.E -long each. The transition from a last waveform of the E.sub.1 waveforms to a first waveform of the S waveforms constitutes a vertical synchronization (V.sub.-- sync) signal. The system a reference event occurring at a first time interval .DELTA.T .sub.1 .+-.Er after said V.sub.-- sync signal, wherein Er stands for time shift error. The system includes filter for filtering the composite video signal so as to obtain a filtered signal. Clamper for clamping the filtered signal so as to obtain a clamped signal. First detector for detecting N (N.ltoreq.S) waveforms in the serration pulses thereby indicating first event occurrence. Second detector for detecting M (M.ltoreq.E.sub.