Abstract: A low-cost and efficient process producing improved organic electronic devices such as transistors that may be used in a variety of applications is described. The applications may include radio frequency identification (RFID) devices, displays and the like. In one embodiment, the improved process is implemented by flash annealing a substrate with an energy having wavelengths ranging from about 250 nm to about 1100 nm or higher. In this flash annealing process energy having wavelengths from about 250 nm to about 350 nm or higher is substantially prevented from irradiating the substrate.

Abstract: A low-cost and efficient process produces self-aligned vias in dielectric polymer films that provides electrical connection between a top conductor and a bottom conductor. The process is achieved by printing conductive posts on the first patterned conductive layer, followed by the deposition of an unpatterned layer dielectric, followed by the deposition of a second patterned conductive layer. The vias are formed during the flash annealing of the post after the dielectric is deposited, but before the second conductive layer is deposited. In this process, the post material is annealed with a flash of light, resulting in a release of energy which removes the dielectric on the top of the post.

Abstract: Dielectric layer pinholes in OFET structures are addressed in a method of fabricating OFET devices through the addition of a high-K dielectric layer to eliminate the effects of shorts in the dielectric layer. The original dielectric layer is maintained such that the semiconductor/dielectric interface remains unchanged. The high-K dielectric layer contributes material to the gate dielectric to plug up pinholes in the original dielectric, but does not contribute significant capacitance due to the high dielectric constant of the additional dielectric layer. The incidence of pinholes in the dielectric layer is reduced without significantly affecting the performance of the OFET transistor.

Abstract: Organic transistors having a nonplanar interface between the insulating layer and the semiconductor layer are provided, along with methods for manufacturing.

Abstract: A method of forming an organic inverter includes providing a first metal layer having a first portion for coupling a source of an OFET to a first power supply voltage, a second portion for coupling a drain of the OFET to an output terminal and a first load resistor terminal, and a third portion for coupling a second load resistor terminal to a second power supply voltage, providing a semiconductor layer for overlapping a portion of the first and second first metal layer portions to form an OFET active area, and for overlapping a portion of the second and third metal layer portions to form a toad resistor, providing a dielectric layer for overlapping the active area of the OFET and the semiconductor area of the load resistor to isolates the first metal layer and semiconductor area from the second metal layer, and providing a second metal layer for overlapping the active area of the OFET to form a gate of the OFET and an input terminal.

Abstract: An OFET includes a thick dielectric layer with openings in the active region of a transistor. After the field dielectric layer is formed, semiconductor ink is dropped in the active region cavities in the field dielectric layer, forming the semiconductor layer. The ink is bounded by the field dielectric layer walls. After the semiconductor layer is annealed, dielectric ink is dropped into the same cavities. As with the semiconductor ink, the field dielectric wall confines the flow of the dielectric ink. The confined flow causes the dielectric ink to pool into the cavity, forming a uniform layer within the cavity, and thereby decreasing the probability of pinhole shorting. After the dielectric is annealed, a gate layer covers the active region thereby completing a high performance OFET structure.

Abstract: A method of forming an organic inverter includes providing a first metal layer having a first portion for coupling a source of a first OFET to a first power supply voltage, a second portion for coupling a drain of the first OFET to an output terminal and to a source of a second OFET, and a third portion for coupling a drain of the second OFET to a second power supply voltage, providing a semiconductor layer for overlapping a portion of the first and second first metal layer portions to form a first OFET active area, and for overlapping a portion of the second and third metal layer portions to form a second OFET active area, providing a dielectric layer for overlapping the active area and isolates the first metal layer and semiconductor layer from the second metal layer, and providing a second metal layer for overlapping the active area of the first OFET to form a gate of the first OFET and an input terminal, and for overlapping the active area of the second OFET to form a floating gate for the second OFET.

Abstract: A low channel length organic field-effect transistor can be produced in high volume and at low cost. The transistor structure includes successively deposited patterned layers of a first conductor layer acting as a source terminal, a first dielectric layer, a second conductor layer acting as a drain terminal, a semiconductor layer, a second dielectric layer, and a third conductor layer acting as the gate terminal. In this structure, the transistor is formed on the edge of the first dielectric between the first conductor layer and the second conductor layer. The second conductor layer is deposited on the raised surfaces formed by the dielectric such that conductive ink does not flow into the trough between the dielectric raised surfaces. This is accomplished by coating a flat or rotary print plate with the conductive ink, and applying the appropriate pressure to deposit the materials only on the raised surfaces of the dielectric. The second metal is automatically aligned to the layer beneath it.

Abstract: A container assembly for tracking a radio frequency identification tag (20) generally includes at least one container (22), an RFID tag (24) associated with the container, and an RFID signal transmitter (26) associated with the radio frequency identification tag. The RFID signal transmitter is capable of transmitting an RFID response signal (1044). The assembly further includes a tracking signal transmitter (28) associated with the RFID signal transmitter. The tracking signal transmitter is capable of transmitting a tracking signal (1046), and the tracking signal is different at least in part from the RFID signal.

Abstract: A low channel length organic field-effect transistor can be produced in high volume and at low cost. The transistor structure includes successively deposited patterned layers of a first conductor layer acting as a source terminal, a first dielectric layer, a second conductor layer acting as a drain terminal, a semiconductor layer, a second dielectric layer, and a third conductor layer acting as the gate terminal. In this structure, the transistor is formed on the edge of the first dielectric between the first conductor layer and the second conductor layer. The second conductor layer is deposited on the raised surfaces formed by the dielectric such that conductive ink does not flow into the trough between the dielectric raised surfaces. This is accomplished by coating a flat or rotary print plate with the conductive ink, and applying the appropriate pressure to deposit the materials only on the raised surfaces of the dielectric. The second metal is automatically aligned to the layer beneath it.

Abstract: A laser ablation method is utilized to define the channel length of an organic transistor. A substrate is coated with a deposition of a metal or conductive polymer deposition, applied in a thin layer in order to enhance the resolution that can be attained by laser ablation. The laser ablation method can be used in a roll-to-roll process, and achieves speeds, volumes, prices and resolutions that are adequate to produce printed electronic technologies.

Abstract: A non-quasistatic MOS frequency divider circuit uses a phase lock loop configuration including an antenna coil to induce a differential input signal, an antenna resonating capacitor, a rectifier, a voltage controlled ring oscillator, a phase detector and a loop filter. All transistors used are organic MOS devices of PMOS, NMOS or both PMOS and NMOS varieties. The voltage-controlled oscillator includes a multiple delay stage ring oscillator. The phase detector includes transistors connected as sampling switches to sample the individual oscillator stage voltages into the loop filter. The sampling transistors have gates connected to the coil. The loop filter provides a substantially direct current to a loop amplifier and then to the voltage controlled oscillator delay control input. This configuration results in the voltage controlled oscillator frequency being synchronous to—and at a sub-multiple of the antenna signal frequency.