Patents Assigned to Orient Semiconductor Electronics Limited
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Patent number: 11462454Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.Type: GrantFiled: January 26, 2021Date of Patent: October 4, 2022Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Jian-De Leu, Guan-Lin Pan
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Patent number: 11462485Abstract: The present disclosure provides an electronic package. The electronic package includes a substrate, an electronic component, a plurality of conductive elements, a metal sheet and a molding layer. The electronic component is disposed on the substrate and electrically connected to the substrate. The conductive elements are disposed on the substrate and electrically connected with the grounding circuit on the substrate. The metal sheet is disposed above the electronic component and is in electrical contact with the conductive elements. The molding layer is formed between the substrate and the metal sheet to enclose the electronic component and the conductive elements. The present disclosure further provides a method of manufacturing the above electronic package.Type: GrantFiled: March 23, 2021Date of Patent: October 4, 2022Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Ying-Chuan Li, Ping-Hua Chu
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Patent number: 11355356Abstract: The method of manufacturing a semiconductor package of the present disclosure includes: providing a redistribution layer having opposing first surface and second surface; disposing a die on the first surface of the redistribution layer and electrically connecting the die to the redistribution layer; forming a mask on the second surface of the redistribution layer; performing a chemical or plasma etching process on the second surface of the redistribution layer to expose the conductive traces in the redistribution layer; removing the mask; and forming a plurality of conductive bumps on the second surface of the redistribution layer and electrically connecting the conductive bumps to the exposed conductive traces in the redistribution layer.Type: GrantFiled: February 2, 2021Date of Patent: June 7, 2022Assignee: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventors: Yueh-Ming Tung, Chia-Ming Yang, Jung-Wei Chen, Jian-De Leu, Guan-Lin Pan
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Patent number: 8627577Abstract: An apparatus of checking dimensions of an object includes a checking platform. The checking platform has a checking slot extending from one side and arriving at another side thereof. The checking slot is defined by a first side wall, a second side wall and a bottom wall, wherein the first side wall has a front section connecting to a rear section. The second side wall has a middle section connecting to a front section and a rear section, wherein the distance between the front section of the first side wall and the front section of the second side wall is greater than that between the rear section of the first side wall and the rear section of the second side wall, and is smaller than that from a connecting location to the middle section of the second side wall.Type: GrantFiled: December 26, 2011Date of Patent: January 14, 2014Assignee: Orient Semiconductor Electronics, LimitedInventor: I Chi Cheng
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Publication number: 20120192445Abstract: An apparatus of checking dimensions of an object includes a checking platform. The checking platform has a checking slot extending from one side and arriving at another side thereof. The checking slot is defined by a first side wall, a second side wall and a bottom wall, wherein the first side wall has a front section connecting to a rear section. The second side wall has a middle section connecting to a front section and a rear section, wherein the distance between the front section of the first side wall and the front section of the second side wall is greater than that between the rear section of the first side wall and the rear section of the second side wall, and is smaller than that from a connecting location to the middle section of the second side wall.Type: ApplicationFiled: December 26, 2011Publication date: August 2, 2012Applicant: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventor: I Chi CHENG
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Publication number: 20120038839Abstract: A micro projector module according to the present invention is provided. The micro projector module includes a substrate, a controller chip, a LCOS chip, a glass and a liquid crystal layer. The controller chip is positioned on the upper surface of the substrate and electrically connected to the substrate. The LCOS chip is positioned on the controller chip and electrically connected to the substrate. The glass is positioned on the LCOS chip and the liquid crystal layer is disposed between the LCOS chip and glass.Type: ApplicationFiled: October 7, 2010Publication date: February 16, 2012Applicant: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventors: Yueh Ming TUNG, Chia Ming YANG, Shu Hui LIN, Yuan Wei LIU, Wei Fang LIN
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Publication number: 20080304245Abstract: A method for discharging an electronic device on a substrate is provided. A metal pin mounted on a wire bonder is used to touch with a specific finger disposed on the substrate which is in electrical connection with the electronic device. As a result, the electric charge previously stored in the electronic device will be conducted to the wire bonder through the specific finger and metal pin thereby discharging the stored charge. Another method for discharging an electronic device on a substrate is also provided. A metal wire protruding out from the capillary of a wire bonder is heated to form a metal ball at the capillary. The capillary is moved to bring the metal ball into contact with the specific finger. As a result, the electric charge previously stored in the electronic device will thus can be discharged to the wire bonder. The present invention further provides a semiconductor package.Type: ApplicationFiled: October 19, 2007Publication date: December 11, 2008Applicant: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventors: Chih Ming CHOU, Yu Jen Wang, Chao Yung Wang, Yu Pin Lin, Chen Ping Su
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Patent number: 7394147Abstract: A semiconductor package includes a substrate, a first chip, a nonconductive adhesive, a second chip and a plurality of supporting balls. The first chip has an upper surface and a lower surface opposite to the upper surface, and the lower surface is mounted on the substrate. The nonconductive adhesive is disposed on the upper surface of the first chip. The second chip has an upper surface and a lower surface opposite to the upper surface, wherein the lower surface is mounted on the upper surface of the first chip by means of the nonconductive adhesive, and the adherent area between the nonconductive adhesive and the second chip is larger than 90% of the area of the lower surface of the second chip. The supporting balls are disposed in the nonconductive adhesive for supporting the second chip.Type: GrantFiled: February 9, 2005Date of Patent: July 1, 2008Assignee: Orient Semiconductor Electronics, LimitedInventors: Kuo Yang Sun, Chia Ming Yang, Hung Yuan Lu, Wei Chin Tsai, Yi Cheng Lin
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Publication number: 20060012040Abstract: A semiconductor package includes a substrate, a first chip, a nonconductive adhesive, a second chip and a plurality of supporting balls. The first chip has an upper surface and a lower surface opposite to the upper surface, and the lower surface is mounted on the substrate. The nonconductive adhesive is disposed on the upper surface of the first chip. The second chip has an upper surface and a lower surface opposite to the upper surface, wherein the lower surface is mounted on the upper surface of the first chip by means of the nonconductive adhesive, and the adherent area between the nonconductive adhesive and the second chip is larger than 90% of the area of the lower surface of the second chip. The supporting balls are disposed in the nonconductive adhesive for supporting the second chip.Type: ApplicationFiled: February 9, 2005Publication date: January 19, 2006Applicant: ORIENT SEMICONDUCTOR ELECTRONICS, LIMITEDInventors: Kuo Sun, Chia Yang, Hung Yu, Wei Tsai, Yi Lin
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Patent number: 6677185Abstract: A method of affixing a heat sink to a substrate and package thereof having a substrate with a position for receiving a semiconductor chip, at least a semiconductor chip for affixing on the position and electrically connecting the substrate, an appropriate thickness of adhesive agent by scraping by means of screen printing technology, a heat sink for covering the semiconductor chip and provided with a plurality of dimples for affixing to the substrate, the method including steps of affixing the semiconductor to the substrate and utilizing a scraper to apply a layer of adhesive agent with an appropriate thickness of adhesive on a platform from the adhesive agent; utilizing a sucker to move the heat sink to a position above the layer of adhesive agent, and dipping the dimples of the heat sink into the adhesive layer so as to adhere some adhesive agent onto the dimples, and then moving the heat sink above the semiconductor chip; affixing the heat sink to the substrate to cover the semiconductor chip; and enclosinType: GrantFiled: June 3, 2002Date of Patent: January 13, 2004Assignee: Orient Semiconductor Electronics LimitedInventors: Hung Chin, Ching-Yi Hu
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Patent number: 6608391Abstract: A preparation method of underfill for flip chip packaging and the device for such method are disclosed. A carrier having a slot at the center thereof is used to hold a substrate having mounted with a plurality of flip chips. The top surface of an upper heat-resistant tape and the bottom surface of a lower heat-resistant tape having the same size are formed into a elongated sealed cavity, and one end of the cavity is injected with fill and the other end is used to extract air so that the underfill is rapidly filled up the cavity between the chips and the substrate, the height of the fillers around the chip can be controlled and will not form bubbles. Thus, the yield and capacity of production are high.Type: GrantFiled: June 5, 2002Date of Patent: August 19, 2003Assignee: Orient Semiconductor Electronics LimitedInventor: Tung-Shen Wu
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Patent number: 6600216Abstract: An improved structure of a pin platform of an integrated circuit having a pin platform body including a chip seat and a plurality of leading plates having their end portions being concentrated on the chip seat and the chip seat being connected to the pin platform body via the connection plate, characterized in that the surrounding of the chip seat is provided with a framing side, and the framing side is connected to a connection plate, and the surface of the chip seat is smaller than the connection surface of the IC to be installed, and the size of the framing side is larger than the size of the connection face of the IC. Therefore, a high performance greenery package is obtained and the ground wire of the IC can be soldered to the framing side, which provides a smooth connection and a communication.Type: GrantFiled: May 6, 2002Date of Patent: July 29, 2003Assignee: Orient Semiconductor Electronics LimitedInventors: Wen-Lo Shieh, Chia-Ming Yang, Chen-Fa Tsai, Shu-Fen Liang, Shu-Min Chou
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Patent number: 6577151Abstract: An inspection device for wiring of integrated circuit includes a base seat and an inspection cover, wherein the top end of the base seat is provided with cavity of appropriate depth and having supporting rib, and the two lateral sides of the cavity are provided with protruded edge a little higher than the cavity; the inspection cover having two side blocks is provided with an extended frame stripe such that the two side blocks and the two frame stripes are formed into a frame body, and corresponding stripes are formed between the two side blocks such that the corresponding stripes divides the frame body into a plurality of observation region, and each observation region is adapted for an inspection plate made from a transparent material, and the two side withholding seat of the inspection plate are located at the end face of the two side blocks, and the inspection plate moves along the end face of the two side blocks, whereby the base plate of the IC is positioned at the withholding protruded edge of the baseType: GrantFiled: November 15, 2002Date of Patent: June 10, 2003Assignee: Orient Semiconductor Electronics LimitedInventors: Chon-Tsai Yang, Chen-Ping Su, Ming-Lang Tsai, Chia-Min Chuang
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Patent number: 6567270Abstract: A semiconductor chip package with cooling arrangement includes a heat sink adapted for covering at least a semiconductor chip, characterized in that said heat sink has an inverted U-shaped cross section thereby forming a recess at an inner bottom thereof adapted for covering at least a semiconductor chip and a plurality of pins extending downwardly from a circumferential lower edge of said heat sink, each of said pins being formed with a neck, an enlarged head, and an open slot separating said neck and said enlarged head into two portions, whereby the package can rapidly remove heat from the semiconductor chip, filter noise and reduce inductance.Type: GrantFiled: November 19, 2001Date of Patent: May 20, 2003Assignee: Orient Semiconductor Electronics LimitedInventors: Wen-Lo Shieh, Ning Huang, Hui-Pin Chen, Hua-Wen Chiang, Chung-Ming Chang, Feng-Chang Tu, Fu-Yu Huang, Hsuan-Jui Chang, Chia-Chieh Hu, Wen-Long Leu
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Patent number: 6499648Abstract: A device for making metal bumps includes a hard conical tubular member having a vertical conical passage at an upper portion thereof, a bell shaped chamber at a lower portion thereof which is larger than the vertical conical passage in diameter, located under and communicated with the vertical conical passage, and a circular recess which is larger than the bell shaped chamber in diameter, located under and communicated with the bell shaped chamber, thereby forming a capillary tube with a surface.Type: GrantFiled: November 19, 2001Date of Patent: December 31, 2002Assignee: Orient Semiconductor Electronics LimitedInventors: Wen-Lo Shieh, Ning Huang, Hui-Pin Chen, Hua-Wen Chiang, Chung-Ming Chang, Feng-Chang Tu, Fu-Yu Huang, Hsuan-Jui Chang, Chia-Chieh Hu, Wen-Long Leu
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Patent number: 6390356Abstract: A method of forming cylindrical bumps on a substrate for integrated circuits includes the steps of: forming copper circuits on a board of a substrate by means of electroplating; covering said board with a screening material; forming openings in said screening material to align with copper circuits on said board, filling pure copper or high melting point metal into said openings by electroplating to form cylindrical projections; forming a layer of solder alloy on an upper end of each of said cylindrical projections to be even with an upper surface of said screening material, and removing said screening material to leave the cylindrical bumps, whereby the engagement operation between the die and the substrate can be facilitated and the manufacture of the die can be easier.Type: GrantFiled: October 23, 2000Date of Patent: May 21, 2002Assignee: Orient Semiconductor Electronics LimitedInventors: Wen Lo Shieh, Fu Yu Huang, Yung-Cheng Chuang, Chia-Chieh Hu, Hui-Pin Chen, Ning Huang, Feng Chang Tu, Chung Ming Chang, Hua Wen Chiang, Hsuan Jui Chang
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Patent number: 6358834Abstract: A method of forming metal bumps on a wafer includes the steps of adhering a heat-resistant and steady synthetic tape on the top of the wafer, punching holes through the synthetic tape to form a blind hole on the synthetic tape above the under-bump-metallurgy layer (UBM), filling solder paste into the blind hole by a pusher, melting and then cooling the solder paste into a solder block removing the synthetic tape to expose the solder block, and melting the solder block to form a ball-shaped solder bump.Type: GrantFiled: October 16, 2000Date of Patent: March 19, 2002Assignee: Orient Semiconductor Electronics LimitedInventors: Wen Lo Shieh, Fu Yu Huang, Yung-Cheng Chuang, Hsuan Jui Chang, Hui-Pin Chen, Ning Huang, Feng-Chang Tu, Chung-Ming Chang, Hua Wen Chiang, Chia-Chieh Hu
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Patent number: 6274491Abstract: A process of manufacturing thin ball array substrates includes the steps of: using a layer of polyimide film as a carrier, electroplating a thin copper layer on the polyimide film, electroplating a thick copper layer on the thin copper layer, applying photosensitive coating layers on both sides of the carrier, mounting two masks with optically transmissible circuit tracks on two sides of the carrier and then processing the carrier with exposure treatment, processing the carrier with development treatment so as to remove the photosensitive coating layers aligned with the circuit track thereby forming recessed circuit tracks on the photosensitive coating layers, electroplating a copper layer on a top of the carrier thereby forming an additional copper layer on the thick copper layer, etching a bottom of the carrier to remove the upper recessed circuit track thereon, coating the copper layer on the upper recessed circuit track with soldering metallic material so as to make a top of the soldering metallic materiaType: GrantFiled: August 11, 2000Date of Patent: August 14, 2001Assignee: Orient Semiconductor Electronics LimitedInventors: Wan Le Xie, Fu Yu Huang, Yung-Cheng Chuang, Ning Huang, Chung Ming Chang, Hui-Pin Chen, Chia-Chieh Hu, Feng Chang Tu, Hsuan Jui Chang, Hua Wen Chiang
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Patent number: D647096Type: GrantFiled: November 8, 2010Date of Patent: October 18, 2011Assignee: Orient Semiconductor Electronics, LimitedInventors: Yueh Ming Tung, Chia Ming Yang, Hsiu Fang Tsai, Shu Hui Lin, Hung Lin Chiang
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Patent number: D647097Type: GrantFiled: November 12, 2010Date of Patent: October 18, 2011Assignee: Orient Semiconductor Electronics, LimitedInventors: Yueh Ming Tung, Chia Ming Yang, Hsiu Fang Tsai, Shu Hui Lin, Hung Lin Chiang