Patents Assigned to ORTHOGONE TECHNOLOGIES INC.
  • Patent number: 10447463
    Abstract: An ultra-low latency communication device includes a clock recovery module, a de-serializer module, an FPGA fabric and a serializer module. The clock recovery module receives an incoming electrical physical layer serial signal and recovers a recovered clock signal therefrom. The de-serializer module converts the incoming electrical physical layer serial signal to an incoming electrical physical layer parallel signal according to driving signals generated based on the recovered clock signal. The FPGA fabric processes the incoming electrical physical layer parallel signal to output an incoming data-link layer parallel signal, receives an outgoing data-link layer parallel signal generated based on electronic information contained in the incoming data-link layer parallel signal, and processes the outgoing data-link layer parallel signal to output an outgoing electrical physical layer parallel signal.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: October 15, 2019
    Assignee: ORTHOGONE TECHNOLOGIES INC.
    Inventor: Alexandre Raymond