Patents Assigned to Osemi, Inc.
  • Integrated transistor devices
    Patent number: 7190037
    Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating oxide layer. A refractory metal gate electrode layer (17) is positioned on upper surface (18) of the second insulating oxide layer.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: March 13, 2007
    Assignee: Osemi, Inc.
    Inventor: Walter David Braddock, IV
  • Junction field effect metal oxide compound semiconductor integrated transistor devices
    Patent number: 7187045
    Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor includes a gate insulating structure comprised of a first conducting oxide layer comprised of indium oxide compounds positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: March 6, 2007
    Assignee: OSEMI, Inc.
    Inventor: Walter David Braddock
  • Metal oxide compound semiconductor integrated transistor devices with a gate insulator structure
    Patent number: 6989556
    Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a gate insulating structure comprised of a first oxide layer that includes a mixture of indium and gallium oxide compounds (30) positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer. Together the lower indium gallium oxide compound layer and the second insulating layer form a gate insulating structure. The gate insulating structure and underlying compound semiconductor layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The first oxide layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating layer and atmospheric contamination.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: January 24, 2006
    Assignee: Osemi, Inc.
    Inventor: Walter David Braddock
  • Integrated transistor devices
    Patent number: 6936900
    Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating oxide layer. A refractory metal gate electrode layer (17) is positioned on upper surface (18) of the second insulating oxide layer.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: August 30, 2005
    Assignee: Osemi, Inc.
    Inventor: Walter David Braddock, IV
  • Metal sulfide-oxide semiconductor transistor devices
    Patent number: 6670651
    Abstract: A self-aligned enhancement mode metal-sulfide-oxide-compound semiconductor field effect transistor (10) includes a lower sulfide layer that is a mixture of Ga2S, Ga2S3, and other gallium sulfide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium sulphur layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium sulfide compound layer and the second insulating layer form a gallium sulfide-oxide gate insulating structure. The gallium sulfide-oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium sulphur layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating sulfide layer.
    Type: Grant
    Filed: August 12, 2000
    Date of Patent: December 30, 2003
    Assignee: Osemi, Inc.
    Inventor: Walter David Braddock