Abstract: Disclosed herein is an ASIC having a base array of function blocks. Each function block includes a plurality of primitive cells. Each primitive cell is defined by a component from a standard cell library. The base array is prefabricated for use later with a custom circuit design.

Abstract: An H-tree is formed in a conducting layer over a base array of a structured ASIC, the H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of a base array and H-tree. The endpoints of an H-tree can be formed at or near sequential elements. When an H-tree is used as part of a clock structure, clock skew to sequential elements and consumption of routing resources for forming a clock structure can be minimized. When a pulse generator is coupled to an H-tree, at least one flip-flop of a plurality of flip-flops can be emulated with an individual latch, thereby increasing effective flip-flop density.

Abstract: Logic blocks for IC designs (including gate-array, standard cell, or logic array designs) provide Design-for-Test-enabled flip-flops (DFT-enabled FFs) that inherently insure compliance with DFT rules associated with scan shifting. Test scan-chains are configured by daisy-chaining instances of the logic block in a transparent (invisible) manner to user-designed application circuits, which can be designed without any user-inserted test structures or other regard for DFT considerations. User asynchronous set and reset inputs and all Stuck-At faults on all user pins on these DFT-enabled FFs are observable via capture and scan-out. A first type of these DFT-enabled FFs features addressable control to partition test the application circuit. A second type of these DFT-enabled FFs features integral capture buffering that eliminates the need for partition test, simplifying control logic and reducing the number of test vectors needed.

Abstract: Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the morphable-devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node population.

Abstract: Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the morphable-devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node populations.