Abstract: A high speed programmable counter architecture is disclosed. In accordance with an embodiment of the present invention, the high speed programmable counter includes an n bit high speed prescaler and an m bit low speed counter. An input signal can be divided by any value equal to or greater than j*2n. The modulus of division can be provided to the programmable counter in binary form directly, without requiring complex calculations or decoding circuitry. The present invention allows high speed programmable counters to be provided that are capable of dividing by much smaller numbers than conventional counters, including numbers less than 2n*(2n−1), wherein n is equal to the number of bits in a high speed prescaler.